參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 117/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Electrical Specifications
105
August 2002 Revised August 2003
SPRS197B
5.2
Recommended Operating Conditions
MIN
1
NOM
1.1
MAX
1.675
UNIT
CVDD
CVDD1/2/3/4/A
DVDD1
DVDD2
Device supply voltage, core
Low Power Standby mode
V
Active mode
1.525
1.6
1.675
Device supply voltage, I/O (Peripheral I/O)
2.5
2.75 or 3.3
3.6
V
Device supply voltage, I/O (USB transceiver)
3
3.3
3.6
V
DVDD3
Device supply voltage, I/O
(MCSI2, McBSP2, GPIO[9:8])
Low-voltage range§
High-voltage range§
Low-voltage range§
High-voltage range§
Low-voltage range§
High-voltage range§
1.65
1.8
1.95
V
2.5
2.75 or 3.3
3.6
DVDD4
Device supply voltage, I/O
(SDRAM interface)
1.65
1.8
1.95
V
2.5
2.75 or 3.3
3.6
DVDD5
Device supply voltage, I/O
(FLASH interface)
Device supply voltage difference
Device supply voltage difference
1.65
1.8
2
V
2.5
2.75 or 3.3
3.6
CVDD DVDD
DVDD CVDD
VSS
1.65
V
2.6
V
Supply voltage, GND
0
V
Standard LVCMOS
0.7 DVDD
0.7 DVDD
2
DVDD
DVDD
DVDD
DVDD
0.3 DVDD
0.3 DVDD
0.8
VIH
High-level input voltage, I/O
Fail-safe LVCMOS
V
USB.DP, DM (mode 1)
I2C
0.7 DVDD
0
Standard LVCMOS
VIL
Low-level input voltage, I/O
Fail-safe LVCMOS
0
V
USB.DP, DM (mode 1)
I2C
0
0
0.3 DVDD
2.5
VI
Input voltage
USB.DP, DM (mode 2)
0.8
V
OSC1 and OSC32K pins
CVDD
VID
Differential input voltage, I/O
USB.DP, DM (mode 2)
200
mV
2-mA drive strength buffers
2
4-mA drive strength buffers
4
IOH
High-level output current
8-mA drive strength buffers
8
mA
18.3-mA drive strength
buffers
18.3
2-mA drive strength buffers
2
4-mA drive strength buffers
4
IOL
Low-level output current
6-mA drive strength buffers
6
mA
8-mA drive strength buffers
8
18.3-mA drive strength
buffers
18.3
TC
All core voltage supplies should be tied to the same voltage level (within 0.3 V).
Low Power Standby is defined as follows: the device is in Deep Sleep mode and LOW_PWR = 1. The device runs from 32 kHz clock in this mode.
§High and low voltage ranges are selectable via software configuration.
In systems where the CVDDx and DVDDx power supplies are ramped at generally the same time (within 500 ms of one another), there are no
specific power sequencing requirements for the supplies. The only sequencing requirement is that the maximum voltage difference between
CVDD and DVDD is not exceeded for greater than 500 ms. Likewise, if different voltages are used for the separate DVDDx supplies, all DVDDx
supplies should be ramp up to valid voltage levels within 500ms of one another.
Operating case temperature
40
85
°
C
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