參數(shù)資料
型號(hào)： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 26/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Introduction
14
August 2002 Revised August 2003
SPRS197B
Table 23. Terminal Characteristics and Multiplexing (Continued)
SUPPLY
RESET
STATE#
OTHER
BUFFER
STRENGTH
PU/
PD
§
DESELECTED
INPUT STATE
MUX CTRL
SETTING
TYPE
SIGNAL NAME
GDY
BALL
GZG
BALL
L14
H12
UART3.RX
I
reg6[5:3] = 000
1
4 mA
B, J
input
PWL
O
reg6[5:3] = 001
NA
DVDD1
DMA_REQ_OBS
O
reg6[5:3] = 010
NA
UART2.RX
I
reg6[5:3] = 011
NA
M20
K16
GPIO15
I/O/Z
reg6[8:6] = 000
NA
PD20
4 mA
J, B, G1
input
DVDD1
KB.R[7]
I
reg6[8:6] = 001
1
N21
K17
GPIO14
I/O/Z
reg6[11:9] = 000
NA
PD20
4 mA
J, B, G1
input
KB.R[6]
I
reg6[11:9] = 001
1
DVDD1
N19
K14
GPIO13
I/O/Z
reg6[14:12] = 000
NA
PD20
4 mA
J, B, G1
input
KB.R[5]
I
reg6[14:12] = 001
1
DVDD1
N18
L15
GPIO12
I/O/Z
reg6[17:15] = 000
NA
PD20
4 mA
J, B, G1
input
MCBSP3.FSX
I/O/Z
reg6[17:15] = 001
0
PD20
DVDD1
N20
L16
GPIO11
I/O/Z
reg6[20:18] = 000
NA
PD20
4 mA
J, B, G1
input
HDQ
I/O
reg6[20:18] = 001
NA
PD20
DVDD1
M15
L17
GPIO7
I/O/Z
reg6[23:21] = 000
NA
PD20
4 mA
J, B, G1
input
MMC.DAT2
I/O/Z
reg6[23:21] = 001
1
DVDD1
P19
K13
GPIO6
I/O/Z
reg6[26:24] = 000
NA
PD20
4 mA
J, B, G1
input
SPI.CS1
O
reg6[26:24] = 001
NA
DVDD1
MCBSP3.FSX
I/O/Z
reg6[26:24] = 010
NA
PD20
P20
L14
GPIO4
I/O/Z
reg6[29:27] = 000
NA
PD20
4 mA
J, B, G1
input
SPI.CS2
O
reg6[29:27] = 001
NA
DVDD1
MCBSP3.FSX
I/O/Z
reg6[29:27] = 010
NA
PD20
P18
K12
GPIO3
I/O/Z
reg7[2:0] = 000
NA
PD20
4 mA
J, B, G1
input
SPI.CS3
O
reg7[2:0] = 001
NA
DVDD1
MCBSP3.FSX
I/O/Z
reg7[2:0] = 010
NA
PD20
LED1
O
reg7[2:0] = 011
NA
M14
M15
GPIO2
I/O/Z
reg7[5:3] = 000
NA
PD20
4 mA
J, B, G1
input
SPI.CLK
O
reg7[5:3] = 001
NA
DVDD1
R19
M17
GPIO1
I/O/Z
reg7[8:6] = 000
NA
PD20
4 mA
J, B, G1
input
UART3.RTS
O
reg7[8:6] = 001
NA
DVDD1
R18
M16
GPIO0
I/O/Z
reg7[11:9] = 000
NA
PD20
4 mA
J, B, G1
input
SPI.RDY
I
reg7[11:9] = 001
NA
DVDD1
USB.VBUS
I
reg7[11:9] = 010
0
PD20
T20
L13
MPUIO5
I/O/Z
reg7[14:12] = 000
NA
PD20
4 mA
J, B, G1
input
LOW_PWR
O
reg7[14:12] = 001
NA
DVDD1
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
§PD20 = 20-
μ
A internal pulldown, PD100 = 100-
μ
A pulldown, PU20 = 20-
μ
A internal pullup, PU100 = 100-
μ
A internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
D = I2C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
|| UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
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