參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 73/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Functional Overview
61
August 2002 Revised August 2003
SPRS197B
Table 320. System DMA Controller Registers
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS
WIDTH
ACCESS
TYPE
RESET
VALUE
FFFE:D800
SYS_DMA_CSDP_CH0
Channel 0 Source/Destination Parameters Register
16
RW
0000h
FFFE:D802
SYS_DMA_CCR_CH0
Channel 0 Control Register
16
RW
0000h
FFFE:D804
SYS_DMA_CICR_CH0
Channel 0 Interrupt Control Register
16
RW
0003h
FFFE:D806
SYS_DMA_CSR_CH0
Channel 0 Status Register
16
R
0000h
FFFE:D808
SYS_DMA_CSSA_L_CH0
Channel 0 Source Start Address Register LSB
16
RW
undef
FFFE:D80A
SYS_DMA_CSSA_U_CH0
Channel 0 Source Start Address Register MSB
16
RW
undef
FFFE:D80C
SYS_DMA_CDSA_L_CH0
Channel 0 Destination Start Address Register LSB
16
RW
undef
FFFE:D80E
SYS_DMA_CDSA_U_CH0
Channel 0 Destination Start Address Register MSB
16
RW
undef
FFFE:D810
SYS_DMA_CEN_CH0
Channel 0 Element Number Register
16
RW
undef
FFFE:D812
SYS_DMA_CFN_CH0
Channel 0 Frame Number Register
16
RW
undef
FFFE:D814
SYS_DMA_CFI_CH0
Channel 0 Frame Index Register
16
RW
undef
FFFE:D816
SYS_DMA_CEI_CH0
Channel 0 Element Index Register
16
RW
undef
FFFE:D818
SYS_DMA_CPC_CH0
Channel 0 Progress Counter Register
16
RW
undef
FFFE:D81A
FFFE:083E
Reserved
FFFE:D840
SYS_DMA_CSDP_CH1
Channel 1 Source/Destination Parameters Register
16
RW
0000h
FFFE:D842
SYS_DMA_CCR_CH1
Channel 1 Control Register
16
RW
0000h
FFFE:D844
SYS_DMA_CICR_CH1
Channel 1 Interrupt Control Register
16
RW
0003h
FFFE:D846
SYS_DMA_CSR_CH1
Channel 1 Status Register
16
R
0000h
FFFE:D848
SYS_DMA_CSSA_L_CH1
Channel 1 Source Start Address Register LSB
16
RW
undef
FFFE:D84A
SYS_DMA_CSSA_U_CH1
Channel 1 Source Start Address Register MSB
16
RW
undef
FFFE:D84C
SYS_DMA_CDSA_L_CH1
Channel 1 Destination Start Address Register LSB
16
RW
undef
FFFE:D84E
SYS_DMA_CDSA_U_CH1
Channel 1 Destination Start Address Register MSB
16
RW
undef
FFFE:D850
SYS_DMA_CEN_CH1
Channel 1 Element Number Register
16
RW
undef
FFFE:D852
SYS_DMA_CFN_CH1
Channel 1 Frame Number Register
16
RW
undef
FFFE:D854
SYS_DMA_CFI_CH1
Channel 1 Frame Index Register
16
RW
undef
FFFE:D856
SYS_DMA_CEI_CH1
Channel 1 Element Index Register
16
RW
undef
FFFE:D858
SYS_DMA_CPC_CH1
Channel 1 Progress Counter Register
16
RW
undef
FFFE:D85A
FFFE:D87E
Reserved
FFFE:D880
SYS_DMA_CSDP_CH2
Channel 2 Source/Destination Parameters Register
16
RW
0000h
FFFE:D882
SYS_DMA_CCR_CH2
Channel 2 Control Register
16
RW
0000h
FFFE:D884
SYS_DMA_CICR_CH2
Channel 2 Interrupt Control Register
16
RW
0003h
FFFE:D886
SYS_DMA_CSR_CH2
Channel 2 Status Register
16
R
0000h
FFFE:D888
SYS_DMA_CSSA_L_CH2
Channel 2 Source Start Address Register LSB
16
RW
undef
FFFE:D88A
SYS_DMA_CSSA_U_CH2
Channel 2 Source Start Address Register MSB
16
RW
undef
FFFE:D88C
SYS_DMA_CDSA_L_CH2
Channel 2 Destination Start Address Register LSB
16
RW
undef
FFFE:D88E
SYS_DMA_CDSA_U_CH2
Channel 2 Destination Start Address Register MSB
16
RW
undef
FFFE:D890
SYS_DMA_CEN_CH2
Channel 2 Element Number Register
16
RW
undef
FFFE:D892
SYS_DMA_CFN_CH2
Channel 2 Frame Number Register
16
RW
undef
FFFE:D894
SYS_DMA_CFI_CH2
Channel 2 Frame Index Register
16
RW
undef
FFFE:D896
SYS_DMA_CEI_CH2
Channel 2 Element Index Register
16
RW
undef
FFFE:D898
SYS_DMA_CPC_CH2
Channel 2 Progress Counter Register
16
RW
undef
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