參數(shù)資料
型號: OMAP5910(DSP)
英文描述: Dual-Core Processor
中文描述: 雙核處理器
文件頁數(shù): 125/160頁
文件大小: 1997K
代理商: OMAP5910(DSP)
Electrical Specifications
113
August 2002 Revised August 2003
SPRS197B
5.8
External Memory Interface Timing
5.8.1 EMIFS/Flash Interface Timing
Table 510 and Table 511 assume testing over recommended operating conditions
(see Figure 57 through
Figure 511).
Table 510. EMIFS/Flash Interface Timing Requirements
NO.
DVDD5 = 1.8 V
Nominal
DVDD5 = 2.75 V
Nominal
DVDD5 = 3.3 V
Nominal
UNIT
MIN
18
MAX
MIN
18
MAX
MIN
15
MAX
F6
tsu(DVCLKH)
Setup time, read data valid
before FLASH.CLK high
Async modes (RT = 0)
Sync Modes (RT = 1)
Async modes (RT = 0)
Sync Modes (RT = 1)
ns
2
2
2
ns
F7
th(CLKHRDV)
Hold time, read data valid
after FLASH.CLK high
29
29
26
ns
2
2
2
ns
When the RT field in the EMIFS configuration register is set, input data is retimed to the external FLASH.CLK signal. RT=1 setting is only valid
in synchronous modes (protocols 1 and 2). For async modes, td(CLKHCSV) with respect to internal FLASH.CLK is given as 0 to allow for other
signals reference to FLASH.CSx. The external FLASH.CLK is disabled for async modes.
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