參數(shù)資料
型號(hào)： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 52/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Functional Overview
40
August 2002 Revised August 2003
SPRS197B
3.3.4 DSP I/O Space Memory Map
The DSP I/O space is a separate address space from the data/program memory space. The I/O space is
accessed via the DSP’s port instructions. The Public and Shared peripheral registers are also accessible by
the MPU through the MPUI (MPU Interface) port. The DSP I/O space is accessed using 16-bit word
addresses. The following tables specify the DSP base addresses where each set of registers is accessed.
All accesses to these registers must utilize the appropriate access width as indicated in the tables. Accessing
registers with the incorrect access width may cause unexpected results including a TI Peripheral Bus (TIPB)
bus error and associated TIPB interrupt.
Refer to Sections 3.16 and 3.17 for more detail about each of these register sets including individual register
addresses, register names, descriptions, supported access types (read, write or read/write) and reset values.
Table 310. DSP Private Peripheral Registers
DSP BASE ADDRESS
REGISTER SET
ACCESS WIDTH
0x00 0C00
DSP DMA Controller Registers
16
0x00 2800
DSP Timer1 Registers
16
0x00 2C00
DSP Timer2 Registers
16
0x00 3000
DSP Timer3 Registers
16
0x00 3400
DSP Watchdog Timer Registers
16
0x00 3800
DSP Interrupt Interface Registers
16
0x00 4800
Level2 Interrupt Handler Registers
16
Table 311. DSP Public Peripheral Registers
DSP BASE ADDRESS
REGISTER SET
ACCESS WIDTH
0x00 8C00
McBSP1 Registers
16
0x00 9000
MCSI2 Registers
16
0x00 9400
MCSI1 Registers
16
0x00 B800
McBSP3 Registers
16
Table 312. DSP/MPU Shared Peripheral Registers
DSP BASE ADDRESS
REGISTER SET
ACCESS WIDTH
0x00 8000
UART1 Registers
8
0x00 8400
UART2 Registers
8
0x00 CC00
UART3 Registers
8
0x00 F000
GPIO Interface Registers
16
0x00 F800
Mailbox Registers
16
Table 313. DSP Configuration Registers
DSP BASE ADDRESS
REGISTER SET
ACCESS WIDTH
0x00 0000
DSP TIPB Bridge Config Registers
16
0x00 0800
DSP EMIF Config Registers
16
0x00 1400
DSP I-Cache Registers
16
0x00 4000
DSP Clock Mode Registers
16
0x00 E400
DSP UART TIPB Bus Switch Registers
16
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