
Introduction
3
August 2002 Revised August 2003
SPRS197B
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication
in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of
the ALUs is under instruction set control, providing the ability to optimize parallel activity and power
consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions
for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources,
and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution
of conditional instructions. The OMAP5910 DSP core also includes a 24K-byte instruction cache to minimize
external memory accesses, improving data throughput and conserving system power.
2.1.1.1
DSP Tools Support
The 55x DSP core is supported by the industry’s leading eXpressDSP
software environment including the
Code Composer Studio
integrated development environment, DSP/BIOS software kernel foundation, the
TMS320
DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio
features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange
(RTDX
), XDS510
emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable
real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a
preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead.
The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of
algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’
extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions
to customers.
2.1.1.2
DSP Software Support
Texas Instruments has also developed foundation software available for the 55x DSP core. The C55x DSP
Library (DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs),
and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over
20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP
code generation tools. These imaging functions support a wide range of applications that include
compression, video processing, machine vision, and medical imaging.
2.1.2 TI-Enhanced TI925T RISC Processor
The MPU core is a TI925T reduced instruction set computer (RISC) processor. The TI925T is a 32-bit
processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core
uses pipelining so that all parts of the processor and memory system can operate continuously.
The MPU core incorporates:
A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
A separate 16K-byte instruction cache and 8K-byte data cache. Both are two-way associative with virtual
index virtual tag (VIVT).
A 17-word write buffer (WB)
The OMAP5910 device uses the TI925T core in little endian mode only.
To reduce effective memory access time, the TI925T has an instruction cache, a data cache, and a write buffer.
In general, these are transparent to program execution.
eXpressDSP, Code Composer Studio, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments.