參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 28/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Introduction
16
August 2002 Revised August 2003
SPRS197B
Table 23. Terminal Characteristics and Multiplexing (Continued)
SUPPLY
RESET
STATE#
OTHER
BUFFER
STRENGTH
PU/
PD
§
DESELECTED
INPUT STATE
MUX CTRL
SETTING
TYPE
SIGNAL NAME
GDY
BALL
GZG
BALL
AA17
R12
MPU_BOOT
I
reg8[29:27] = 000
NA
PD20
4 mA
J, B
input
MCBSP3_DR
I
reg8[29:27] = 001
NA
PD20
DVDD1
USB1_SUSP
O
reg8[29:27] = 010
NA
P14
U13
RST_HOST_OUT
O
reg9[2:0] = 000
NA
4 mA
J, A, G1
0
MCBSP3.DX
O
reg9[2:0] = 001
NA
DVDD1
USB1.SE0
O
reg9[2:0] = 010
NA
W16
P14
pin forced to high-z
Z
reg9[5:3] = 000
NA
PD20
4 mA
J, A, G1
Z
MCBSP3.CLKX
I/O/Z
reg9[5:3] = 001
NA
PD20
DVDD1
USB1.TXEN
O
reg9[5:3] = 010
NA
V15
P12
MPU_RST
I
NA
NA
J, B
input
DVDD1
DVDD1
W15
M11
RST_OUT
O
NA
NA
4 mA
J, A
0
AA15
U12
pin forced to drive low
O
reg9[14:12] = 000
NA
2 mA
J, A, G1
0
UART1.RTS
O
reg9[14:12] = 001
NA
DVDD1
R14
M10
UART1.CTS
I
NA
NA
PD20
J, B
input
DVDD1
DVDD1
DVDD1
V14
R11
UART1.RX
I
NA
NA
PD20
J, B
input
Y14
P13
pin forced to drive low
O
reg9[23:21] = 000
NA
2 mA
J, A, G1
0
UART1.TX
O
reg9[23:21] = 001
NA
W14
N12
MCSI1.DOUT
O
reg9[26:24] = 000
NA
2 mA
H1
0
USB1.TXD
O
reg9[26:24] = 001
reg9[26:24] = 001||
NA
J, A, G1,
DVDD1
UART1.TX
O
NA
R13
L10
BCLKREQ
I
reg9[29:27] = 000
0
PD20
J, B
input
UART3.CTS
I
reg9[29:27] = 001
0
PD20
DVDD1
UART1.DSR
I
reg9[29:27] = 010
1
PD20
Y13
P11
BCLK
O
regA[2:0] = 000
NA
4 mA
J, A, G1
0
UART3.RTS
O
regA[2:0] = 001
NA
DVDD1
UART1.DTR
O
regA[2:0] = 010
NA
V13
T11
MCSI1.SYNC
I/O/Z
regA[5:3] = 000
0
PD20
2 mA
J, B, G1
input
USB1.VP
I
regA[5:3] = 001
NA
PD20
DVDD1
AA13
U11
MCSI1.CLK
I/O/Z
regA[8:6] = 000
0
PD20
2 mA
J, B, G1
input
USB1.VM
I
regA[8:6] = 001
regA[8:6] = 001||
0
PD20
DVDD1
UART1.RX
I
0
PD20
W13
R10
MCSI1.DIN
I
regA[11:9] = 000
NA
PD20
J, B
input
USB1.RCV
I
regA[11:9] = 001
regA[11:9] = 001||
0
PD20
DVDD1
UART1.CTS
I
0
PD20
Y12
N10
CLK32K_OUT
O
regA[14:12] = 000
NA
8 mA
J, A
LZ
MPUIO0
I/O/Z
regA[14:12] = 001
NA
DVDD1
USB1.SPEED
O
regA[14:12] = 010
NA
P13
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
§PD20 = 20-
μ
A internal pulldown, PD100 = 100-
μ
A pulldown, PU20 = 20-
μ
A internal pullup, PU100 = 100-
μ
A internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
D = I2C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
|| UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
N9
CLK32K_IN
I
NA
NA
J, B
input
DVDD1
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
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