參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 151/160頁
文件大小： 1997K
代理商： OMAP5910(DSP)
Electrical Specifications
139
August 2002 Revised August 2003
SPRS197B
5.14 I
2
C Timings
Table 530 assumes testing over recommended operating conditions (see Figure 533).
Table 530. I
2
C Signals (I2C.SDA and I2C.SCL) Switching Characteristics
NO.
PARAMETER
STANDARD
MODE
FAST
MODE
UNIT
MIN
10
MAX
MIN
MAX
IC1
tc(SCL)
Cycle time, I2C.SCL
2.5
μ
s
IC2
tsu(SCLH-SDAL)
Setup time, I2C.SCL high before I2C.SDA low (for a repeated START
condition)
4.7
0.6
μ
s
IC3
th(SCLL-SDAL)
Hold time, I2C.SCL low after I2C.SDA low (for a repeated START
condition)
4
0.6
μ
s
IC4
tw(SCLL)
tw(SCLH)
tsu(SDA-SDLH)
th(SDA-SDLL)
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
tsu(SCLH-SDAH)
tw(SP)
Cb§
Pulse duration, I2C.SCL low
4.7
1.3
μ
s
μ
s
ns
μ
s
μ
s
IC5
Pulse duration, I2C.SCL high
4
0.6
IC6
Setup time, I2C.SDA valid before I2C.SCL high
Hold time, I2C.SDA valid after I2C.SCL low (for I2C bus devices)
250
100
IC7
0
0
0.9
IC8
Pulse duration, I2C.SDA high between STOP and START conditions
4.7
1.3
IC9
Rise time, I2C.SDA
1000
300
ns
IC10
Rise time, I2C.SCL
1000
300
IC11
Fall time, I2C.SDA
300
300
ns
IC12
Fall time, I2C.SCL
300
300
IC13
Setup time, I2C.SCL high before I2C.SDA high (for STOP condition)
4.0
0.6
μ
s
ns
IC14
Pulse duration, spike (must be suppressed)
0
50
IC15
Capacitive load for each bus line
400
400
pF
In the master-only I2C operating mode of OMAP5910, minimum cycle time for I2C.SCL is 12
μ
s.
The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the low period (tw(SCLL)) of the I2C.SCL signal.
§Cb = The total capacitance of one bus line in pF.
IC10
IC8
IC4
IC3
IC7
IC12
IC5
IC6
IC14
IC13
IC2
IC3
Stop
Start
Repeated
Start
Stop
I2C.SDA
I2C.SCL
IC1
NOTES: A. A device must internally provide a hold time of at least 300 ns for the I2C.SDA signal (referred to the VIHmin
of the I2C.SCL signal
)
to bridge the undefined region of the falling edge of I2C.SCL.
B. The maximum th(SCLLSDAL)
has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the I2C.SCL signal.
C. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDASDLH)
250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the I2C.SCL signal. If such a device
does stretch the LOW period of the I2C.SCL signal, it must output the next data bit to the I2C.SDA line tr max + tsu(SDASDLH) =
1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the I2C.SCL line is released.
D. Cb
= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall times are allowed.
Figure 533. I
2
C Timings
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