參數(shù)資料
型號: OMAP5910(DSP)
英文描述: Dual-Core Processor
中文描述: 雙核處理器
文件頁數(shù): 49/160頁
文件大小: 1997K
代理商: OMAP5910(DSP)
Functional Overview
37
August 2002 Revised August 2003
SPRS197B
3.2.2 MPU Subsystem Registers Memory Map
The MPU accesses peripheral and configuration registers in the same way that internal and external memory
is accessed. The following tables specify the MPU base addresses where each set of registers is accessed.
All accesses to these registers must utilize the appropriate access width (8-, 16-, or 32-bit-wide accesses) as
indicated in the tables. Accessing registers with the incorrect access width may result in unexpected results
including a TI Peripheral Bus (TIPB) bus error and associated TIPB interrupt.
Refer to Sections 3.15, 3.16, and 3.17 for more detail about each of these register sets including individual
register addresses, register names, descriptions, supported access types (read, write or read/write) and reset
values.
Table 32. MPU Private Peripheral Registers
MPU BASE ADDRESS
REGISTER SET
ACCESS
WIDTH
0xFFFE 0000
MPU Level 2 Interrupt Handler Registers
32
0xFFFE C000
LCD Controller Registers
32
0xFFFE C500
MPU Timer1 Registers
32
0xFFFE C600
MPU Timer2 Registers
32
0xFFFE C700
MPU Timer3 Registers
32
0xFFFE C800
MPU Watchdog Timer Registers
32
0xFFFE CB00
MPU Level 1 Interrupt Handler Registers
32
0xFFFE D800
System DMA Controller Registers
16
Table 33. MPU Public Peripheral Registers
MPU BASE ADDRESS
REGISTER SET
ACCESS
WIDTH
0xFFFB 1000
McBSP2 Registers
16
0xFFFB 3000
Microwire Registers
I2C Registers
16
0xFFFB 3800
16
0xFFFB 4000
USB Function Registers
16
0xFFFB 4800
RTC Registers
8
0xFFFB 5000
MPUIO/Keyboard Registers
16
0xFFFB 5800
Pulse Width Light (PWL) Registers
8
0xFFFB 6000
Pulse Width Tone (PWT) Registers
8
0xFFFB 6800
Camera Interface Registers
32
0xFFFB 7800
MMC/SD Registers
16
0xFFFB 9000
Timer 32k Registers
32
0xFFFB A000
USB Host Registers
32
0xFFFB A800
Frame Adjustment Counter (FAC) Registers
16
0xFFFB C000
HDQ/1-Wire Registers
8
0xFFFB D000
LED Pulse Generator 1 (LPG1) Registers
8
0xFFFB D800
LED Pulse Generator 2 (LPG2) Registers
Table 34. MPU/DSP Shared Peripheral Registers
8
MPU BASE ADDRESS
REGISTER SET
ACCESS
WIDTH
0xFFFB 0000
UART1 Registers
8
0xFFFB 0800
UART2 Registers
8
0xFFFB 9800
UART3 Registers
8
0xFFFC E000
GPIO Interface Registers
16
0xFFFC F000
Mailbox Registers
16
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