參數(shù)資料
型號(hào)： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 142/160頁
文件大小： 1997K
代理商： OMAP5910(DSP)
Electrical Specifications
130
August 2002 Revised August 2003
SPRS197B
Table 520. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
NO.
MIN
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
M49
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, MCBSPx.DR valid before MCBSPx.CLKX high
15
2 2P
ns
M50
Hold time, MCBSPx.DR valid after MCBSPx.CLKX high
2
6 + 6P
ns
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX low
McBSP1
21
M51
tsu(FXL-CKXL)
McBSP2
5
ns
McBSP3
10
M52
tc(CKX)
Cycle time, MCBSPx.CLKX
2P
16P
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
Table 521. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
NO.
PARAMETER
MASTER§
SLAVE
UNIT
MIN
MAX
MIN
MAX
M43
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXL-DXV)
td(FXL-DXV)
Hold time, MCBSPx.FSX low after MCBSPx.CLKX high
Delay time, MCBSPx.FSX low to MCBSPx.CLKX low#
0.45T
0.55T
ns
M44
0.45D
0.55D
ns
M45
Delay time, MCBSPx.CLKX low to MCBSPx.DX valid
1
7
3P + 2
5P + 18
ns
M48
Delay time, MCBSPx.FSX low to MCBSPx.DX valid
4P + 18
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
§T =
CLKX period = (1 + CLKGDV) * P
D =
CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (MCBSPx.CLKX).
M51
M50
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
MCBSPx.CLKX
MCBSPx.FSX
MCBSPx.DX
MCBSPx.DR
M44
M48
M45
M49
M43
LSB
M52
MSB
Figure 522. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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