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參數(shù)資料
| 型號(hào)： | OMAP5910(DSP) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁數(shù)： | 63/160頁 |
| 文件大小： | 1997K |
| 代理商： | OMAP5910(DSP) |
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Functional Overview
51
August 2002 Revised August 2003
SPRS197B
3.9
System DMA Controller
The System Direct Memory Access (DMA) controller transfers data between points in the memory space
without intervention by the MPU. The System DMA allows movements of data to and from internal memory,
external memory, and peripherals to occur in the background of MPU operation. It is designed to off-load the
block data transfer function from the MPU processor. The System DMA is configured by the MPU via the MPU
private peripheral bus.
The System DMA controller has nine independent general-purpose channels and seven ports that it may
transfer to/from. An additional tenth channel is dedicated for use with the LCD controller. Of the seven
available ports, the DMA transfers may occur between any two ports with the exception of the LCD port, which
may only be used as a destination with the EMIFF or IMIF as the source. For maximum transfer efficiency,
all nine channels are independent. This means that if multiple channels are exclusively accessing different
ports, then simultaneous transfers performed by the channels will occur uninhibited. If the multiple channels
are accessing common ports, however, some arbitration cycles will be necessary. Arbitration occurs in a
round-robin fashion with configurable priority for each channel (high or low).
The basic functional features of the system DMA controller are as follows:
Nine general-purpose and one dedicated (LCD) DMA channels
Round-robin arbitration scheme with programmable priorities
Concurrent DMA transfer capability
Start of transfer on peripheral request or host request
Byte-alignment and Byte-packing/unpacking capability
Burst transfer capability (IMIF, EMIFF, EMIFS, LCD, and Local ports)
Time-out counter for each DMA channel to prevent a channel locking on a memory location or peripheral.
Constant, post-incrementing, and Single- or Double-Indexed addressing modes
Autoinitialization for multiple block transfers without MPU intervention
Access available to all of the memory range (physical memory mapping and TIPB space)
Seven ports are available for different kinds of hardware resources.
EMIFS port (allowing access to external asynchronous memory or devices)
EMIFF port (allowing access to external SDRAM)
IMIF port (allowing access to 192K bytes of shared SRAM)
MPUI port (allowing access to DSP memory and peripherals)
TIPB port (allowing peripheral register access)
Local port (used for Host USB only)
LCD port (allowing transfers to the LCD controller)
Memory-to-memory transfer granularity of 8, 16, and 32 bits.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| OMAP5910GGZG1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| OMAP5910JGDY1R | 功能描述:IC OMAP DUAL-CORE PROC 289-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:OMAP-59xx 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| OMAP5910JGDY2 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Applications Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| OMAP5910JGZG1 | 制造商:Texas Instruments 功能描述: |
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