參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 118/160頁
文件大小： 1997K
代理商： OMAP5910(DSP)
Electrical Specifications
106
August 2002 Revised August 2003
SPRS197B
5.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
DVDD
= 3.3 V, IOH = MAX
DVDD
= 3.3 V, IOH = MAX
IO = 12 mA
DVDD
= 3.3 V, IOL = MAX
DVDD
= 3.3 V, IOL = MAX
IO = 12 mA
Fast mode at 6-mA load
MIN
TYP
MAX
UNIT
High-level output
voltage
Standard LVCMOS
0.8 DVDD
0.8 DVDD
DVDD 0.5
VOH
Fail-safe LVCMOS
V
USB.DP, DM
Standard LVCMOS
0.22 DVDD
0.22 DVDD
Fail-safe LVCMOS
Low-level output
voltage
USB.DP, DM
0.5
VOL
0.6
V
I2C
Fast mode at 3-mA load
0.4
Standard mode at 3-mA
load
0.4
Fail-safe LVCMOS inputs
without internal
pullups/pulldowns enabled
VI = VI MAX to VI MIN
20
20
Other Inputs without internal
pullups/pulldowns enabled
VI = VI MAX to VI MIN
1
1
II
Input current
Input pins with 20-
μ
A
pulldowns enabled
DVDD
= MAX,
VI = VSS to VDD
DVDD
= MAX,
VI = VSS to VDD
CVDD
= MAX,
VI = VSS to VDD
DVDD
= MAX,
VI = VSS to VDD
6
20
60
μ
A
Input pins with 100-
μ
A
pulldowns enabled
30
100
300
Input pins with 20-
μ
A
pullups enabled
60
20
6
Input pins with 100-
μ
A
pullups enabled
20
100
30
IOZ
Input current for outputs in high-impedance
20
20
μ
A
IDDC (Q)
Core voltage supply current, quiescent
Sum of CVDDx currents.
(Deep sleep mode
with CVDD = 1.6V)
Sum of CVDDx currents.
(Deep sleep mode
with CVDD = 1.1V)
Sum of CVDDx currents
(Case 1).
115
50
μ
A
IDDC (A)
Core voltage supply current, active
150
mA
Sum of CVDDx currents
(Case 2).
170
mA
IDDCP A)
Core and I/O voltage supply current, active
Sum of CVDDx and DVDDx
currents (Case 3§).
45
mA
Sum of CVDDx and DVDDx
currents (Case 4).
6
mA
Ci
Input capacitance
USB.DP,DM
7
pF
All other I/O pins
4
CO
Output capacitance
USB.DP,DM
All other I/O pins
7
4
pF
Case 1: MPU running OS, DSP running GSM Vocoder from internal memory, DSP MMU and all clock domains active, no LCD activity.
Case 2: Same conditions as Case 1 only DSP running from external memory with I-cache enabled.
§Case 3: Only LCD activity (MPU and DSP idled with clocks off). LCD running 320x240 TFT at 70 Frames per second with frame buffer in internal
memory (DPLL at 120MHz).
Case 4: Same as Case 3 only LCD running at 10 Frames per second with DPLL at 6MHz.
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