參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 27/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Introduction
15
August 2002 Revised August 2003
SPRS197B
Table 23. Terminal Characteristics and Multiplexing (Continued)
SUPPLY
RESET
STATE#
OTHER
BUFFER
STRENGTH
PU/
PD
§
DESELECTED
INPUT STATE
MUX CTRL
SETTING
TYPE
SIGNAL NAME
GDY
BALL
GZG
BALL
T19
N15
MPUIO4
I/O/Z
reg7[17:15] = 000
NA
PD20
4 mA
J, B, G1
input
EXT_DMA_REQ1
I
reg7[17:15] = 001
NA
DVDD1
LED2
O
reg7[17:15] = 010
NA
N15
N17
MPUIO2
I/O/Z
reg7[20:18] = 000
NA
PD20
4 mA
J, B, G1
input
EXT_DMA_REQ0
I
reg7[20:18] = 001
NA
DVDD1
U19
M14
MPUIO1
I/O/Z
NA
NA
4 mA
B, J
input
DVDD1
DVDD1
DVDD1
T18
P15
I2C.SCL
I/O/Z
NA
NA
6 mA
J, D, H1
Z
V20
N14
I2C.SDA
I/O/Z
NA
NA
6 mA
J, D, H1
Z
U18
P17
UWIRE.SDI
I
reg8[2:0] = 000
NA
PD20
4 mA
B, J
input
UART3.DSR
I
reg8[2:0] = 001
1
PD20
DVDD1
UART1.DSR
I
reg8[2:0] = 010
1
PD20
MCBSP3.DR
I
reg8[2:0] = 011
NA
PD20
W21
P16
UWIRE.SDO
O
reg8[5:3] = 000
NA
4 mA
J, A, G1
0
UART3.DTR
O
reg8[5:3] = 001
NA
DVDD1
UART1.DTR
O
reg8[5:3] = 010
NA
MCBSP3.DX
O
reg8[5:3] = 011
NA
V19
M13
UWIRE.SCLK
O
reg8[8:6] = 000
NA
4 mA
J, A, G1
0
KB.C[7]
O
reg8[8:6] = 001
NA
DVDD1
N14
R16
pin forced to high-z
Z
reg8[11:9] = 000
NA
4 mA
J, A
Z
UWIRE.CS0
O
reg8[11:9] = 001
NA
DVDD1
MCBSP3.CLKX
I/O/Z
reg8[11:9] = 010
NA
P15
L12
pin forced to high-z
Z
reg8[14:12] = 000
NA
4 mA
J, A
Z
UWIRE.CS3
O
reg8[14:12] = 001
NA
DVDD1
KB.C[6]
O
reg8[14:12] = 010
NA
W19
R14
BFAIL/EXT_FIQ
I
NA
NA
J, B
input
DVDD1
DVDD1
DVDD1
AA20
T15
CLK32K_CTRL
I
NA
NA
J, B
input
V18
T16
CONF
I
NA
NA
PD10
0
A
input
Y19
U17
TDI
I
NA
NA
PD20
B
input
DVDD1
DVDD1
DVDD1
DVDD1
DVDD1
AA19
U16
TDO
O
NA
NA
4 mA
A
0
V17
R13
TMS
I
NA
NA
PD20
B
input
W18
T14
TCK
I
NA
NA
PD20
B
input
Y18
U15
TRST
I
NA
NA
PD10
0
B
input
V16
R17
EMU0
I/O/Z
NA
NA
PU10
0
2 mA
B
Z
DVDD1
W17
T13
EMU1
I/O/Z
NA
NA
PU10
0
2 mA
B
Z
DVDD1
Y17
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
§PD20 = 20-
μ
A internal pulldown, PD100 = 100-
μ
A pulldown, PU20 = 20-
μ
A internal pullup, PU100 = 100-
μ
A internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
D = I2C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
|| UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
U14
STAT_VAL/WKUP
I
NA
NA
A
input
DVDD1
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
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