參數(shù)資料
型號: OMAP5910(DSP)
英文描述: Dual-Core Processor
中文描述: 雙核處理器
文件頁數(shù): 144/160頁
文件大?。?/td> 1997K
代理商: OMAP5910(DSP)
Electrical Specifications
132
August 2002 Revised August 2003
SPRS197B
5.10 Multichannel Serial Interface (MCSI)
Table 524 and Table 525 assume testing over recommended operating conditions (see Figure 524 and
Figure 525).
Table 524. MCSI Timing Requirements
NO.
MIN
MAX
B
0.55P
0.55P
UNIT
MC11
fop(CLK)
tw(CLKH)
tw(CLKL)
tr(CLK)
tf(CLK)
tsu(FSH-CLKL)
th(CLKL-FSH)
Operating frequency, MCSIx.CLK
Slave
MHz
MC12
Pulse duration, MCSIx.CLK high
Slave
0.45P
0.45P
ns
MC13
Pulse duration, MCSIx.CLK low
Slave
ns
MC14
Rise time, MCSIx.CLK
Slave
12
ns
MC15
Fall time, MCSIx.CLK
Slave
12
ns
MC16
MC17
Setup time, external MCSIx.SYNC high before MCSIx.CLK low
Hold time, external MCSIx.SYNC high after MCSIx.CLK low
Slave
Slave
Master
18
6
27
ns
ns
MC18
tsu(DIV-CLKL)
Setup time, MCSIx.DIN valid before MCSIx.CLK low
ns
Slave
18
MC19
th(CLKL-DIV)
Hold time, MCSIx.DIN valid after MCSIx.CLK low
Master
Slave
0
6
ns
P = MCSIx.CLK period [tc(CLK)] in nanoseconds.
B = Base frequency for OMAP5910 (12 or 13 MHz).
Table 525. MCSI Switching Characteristics
NO.
PARAMETER
MIN
MAX
0.5B
0.55P
0.55P
UNIT
MC1
fop(CLK)
tw(CLKH)
tw(CLKL)
td(CLKH-FS)
Operating frequency, MCSIx.CLK
Master
MHz
MC2
Pulse duration, MCSIx.CLK high
Master
0.45P
0.45P
ns
MC3
Pulse duration, MCSIx.CLK low
Master
ns
MC4
Delay time, MCSIx.CLK high to MCSIx.SYNC transition
Master
Master
0
0
5
5
ns
MC7
td(CLKH-DOV)
Delay time, MCSIx.CLK high to MCSIx.DOUT valid
ns
Slave
2
30
MC8
ten(CLKH-DO)
Enable time, MCSIx.DOUT driven from MCSIx.CLK high
Master
Slave
0
2
ns
P = MCSIx.CLK period [tc(CLK)] in nanoseconds.
B = Base frequency for OMAP5910 (12 or 13 MHz).
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