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參數(shù)資料
| 型號： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁數(shù)： | 92/222頁 |
| 文件大小： | 974K |
| 代理商： | CD2481 |
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CD2481
—
Programmable Four-Channel Communications Controller
92
Datasheet
7.6
Bisync Protocol
In both transmit and receive, the CD2481 interprets the first characters of data to determine the
type of frame and compile the corresponding BCC. The host uses COR1 to program parity options
and character length, and COR2 to program the character set (ASCII or EBCDIC) and determine
whether to use CRC-16 or LRC.
7.6.1
Bisync Transmit Processing
The CD2481 can be programmed to idle in either SYN or mark. When idling in mark, a
programmable number of leading pad characters can be transmitted before each data frame. The
leading pads ensure the Remote Phase locked loop has sufficient transitions to achieve bit
synchronization before data starts. The leading pad character can be programmed as AA (suitable
for NRZ and Manchester), or 00 (suitable for NRZI).
When data is available in the FIFO, transmission will be started; any required leading pads will be
sent, followed by a SYN pair and the CPU-supplied data. The CD2481 monitors the transmit data
to determine frame type and compute the correct BCC, eliminating unnecessary characters from
the calculation. If SYN sequences are embedded in the data supplied by the CPU, they will be
transmitted
—
but excluded
—
from the BCC calculation.
If a frame transmission is aborted via the STCR, an EOT and trailing pad will be transmitted and
the line returned to its idle state. A frame is terminated normally when an EOF indication is passed
to the CD2481, either in TEOIR, or in the A/BTBSTS. If the frame ends with an EOT or ENQ
condition, the trailing pad is appended and transmission is complete; otherwise, any accumulated
BCC is appended, followed by the trailing pad, and the line returned to its idle state.
7.6.2
Bisync Receive Processing
After initialization, the receiver starts in Synchronous Hunt Mode, and will discard data until a pair
of SYN characters are detected. The next non-SYN data is assumed to be the start of frame. The
receive data is continuously monitored to determine the type of frame (transparent/non-transparent,
BCC/no BCC). If required, the BCC is compiled, excluding any characters which should not be
part of the calculation. When a frame terminating condition is detected, and if a BCC was
accumulated, it is checked and the EOF information passed to the CPU via the RISRl. If the frame
is terminated with an ENQ condition, the BCC is not checked, and an abort indication is passed to
the CPU in RISRl.
An extra frame termination process is available by programming an extra-frame-termination
character into COR6. When this character is detected, the receive frame is terminated immediately,
and no BCC is computed. Following an initialize channel command, the COR6 is set to the value
of DLE (10hex) by the internal code; the user may alter this to any other value. To detect the
condition where the frame termination character has been corrupted on a non-transparent line,
COR6 can be programmed to the idle condition FF hex. To use this on a transparent line, the data
should not equal FF; if the value in COR6 is preceded by the DLE character, it does not cause
frame termination.
Short Frame Processing
Short frames in Bisync mode are generally terminated with minimum two bytes of x
’
FF. The
CD2481 reports these frames as follows:
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