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參數(shù)資料
| 型號(hào)： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁數(shù)： | 44/222頁 |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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CD2481
—
Programmable Four-Channel Communications Controller
44
Datasheet
an equal chance of getting its interrupts through as the CD2481 that is nearest to the top of the
interrupt chain. The Fair Share scheme is totally transparent to the user, and no enabling or
disabling is required.
When an interrupt request line is asserted, the Fair bit for that type of interrupt on the asserting
device is cleared. The Fair bit remains cleared until the interrupt line returns to a high state. The
CD2481 does not assert a new interrupt of that type while the corresponding Fair bit is cleared.
Therefore, when multiple CD2481s assert interrupts together, each one is serviced in turn, before
they can reassert the same interrupt type.
The IREQn* interrupt request lines are open-drain outputs that can be tied together in groups of the
same type, creating a Fair Share scheme for each group of interrupts. Alternatively, all three groups
can be tied to a common request and using the CD2481 internal automatic priority scheme (see
Section 5.2.4.1
).
5.3
FIFO and Timer Operations
Each channel in the CD2481 has a 16-byte receive FIFO and a 16-byte transmit FIFO. The FIFOs
are accessible through the RDR (Receive Data register) and TDR (Transmit Data register)
registers. These Virtual registers are shared among the four channels; therefore, they can not be
accessed outside of an interrupt context.
Each channel
’
s threshold level is common for both FIFOs. It is set by COR4 (Channel Option
Register 4), with a maximum threshold value of 12. The FIFO threshold is meaningful in both
DMA and non-DMA modes. In DMA mode, the FIFO threshold determines when transfer bursts
will occur. In non-DMA mode, the threshold level determines when transfer interrupts are asserted.
5.3.1
Receive FIFO Operation
In the Asynchronous mode, a Good Data
interrupt is initiated when the number of characters in
the FIFO is greater than the FIFO threshold. Note that receive time-out and receive data exception
conditions also cause an interrupt from the device.
In the Synchronous mode, an interrupt request for data transfer is initiated when either the number
of characters is greater than the FIFO threshold or an end of frame has been received.
5.3.2
Transmit FIFO Operation
The TxDat and TxEmpty bits in the IER control the generation of transmit FIFO interrupts. The
CD2481 initiates an interrupt request for more data when the number of empty bytes in the FIFO is
greater than the threshold set by COR4. During synchronous operation, when the last byte of the
frame is transferred to the FIFO, the CD2481 stops asserting transmit interrupts until the frame is
sent, including the FCS and closing flag, if any.
5.3.3
Timers
The global TPR (Timer Period register) provides a timer prescale
‘
tick
’
as a clock source for the
various timers in the device. The TPR counter is clocked by the system clock (CLK) divided by
2048. To maintain timer accuracy, the TPR register should not be programmed with a value not
less than 16 (10 hex)
—
a
‘
tick
’
of about 1 millisecond when CLK is 33 MHz.
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