
Programmable Four-Channel Communications Controller
—
CD2481
Datasheet
131
Bit 4
Reserved
–
must be zero.
Bits 3:0
FIFO Threshold in characters
Note that the maximum value allowed for this field is 12 (0C hex). This 4-bit binary
encoded field, sets the FIFO transfer threshold for both transmit and receive FIFOs
for both Interrupt and DMA Transfer modes.
In Asynchronous mode, a Good Data transfer is initiated for the number of charac-
ters in the FIFO greater than the specified threshold. Receive time-out and the occur-
rence of a receive data exception are also cause to initiate a receive transfer. In
Synchronous modes, data transfer is initiated when the number of characters in the
FIFO is greater than the specified threshold. An end of frame also initiates a receive
transfer.
For transmit operation, the CD2481 attempts to refill the transmit FIFO when the
empty space in the FIFO is greater than the set threshold. In synchronous frame
transmissions, the CD2481 stops refilling the transmit FIFO once the last character
in the frame has been transferred to the FIFO.
9.2.6
Channel Option Register 5 (COR5)
This register is used to define the current-state change options to be monitored.
Bit 7
DSRod = 1
Detect zero-to-one transition on DSR input (one-to-zero transition of DSR (MSVR)
bit)
Bit 6
CDod = 1
Detect zero-to-one transition on CD input (one-to-zero transition of CD (MSVR) bit)
Bit 5
CTSod = 1
Detect zero-to-one transition on CTS input (one-to-zero transition of CTS (MSVR)
bit)
Bit 4
In/Out
–
Automatic receive flow control select
This bit is ignored when bits 3:0 are all zeros.
0 = Use out-of-band flow control (DTR pin).
1 = Use in-band flow control (automatic transmission of XOFF/XON characters)
Register Name: COR5
Register Description: Channel Option Register 5
Default Value: x
’
00
Access: Byte Read/Write
Intel Hex Address: x
’
17
Motorola Hex Address: x
’
14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DSRod
CDod
CTSod
In/Out
Rx Flow Control Threshold