
CD2481
—
Programmable Four-Channel Communications Controller
188
Datasheet
9.6.4.9
Receive Current Buffer Address Lower (RCBADRL)
9.6.4.10
Receive Current Buffer Address Upper (RCBADRU)
These registers contain the address of the current DMA buffer being used for receive data, updated
at the end of receive data transfers. These registers are for the private use of the CD2481 to manage
DMA transfers. In Asynchronous mode, the host can read this register during a receive exception
interrupt to determine how much data is in the buffer. The address is the location of the next
character to be transferred to the buffer. The host needs that information to process newly arrived
data in the buffer if it is being used in the Append mode, and the data time-out has occurred. It is
also needed if an exception has occurred, and a gap is to be left in the FIFO for the insertion of
status information by the host. In the case of a bus error during receive data transfer, this register
provides the start address of the transfer causing the bus error.
Register Name: RCBADRL
Register Description: Current Receive Buffer Address, lower word
Default Value: x
’
0000
Access: Word Read Only
Intel Hex Address: x
’
3C
Motorola Hex Address: x
’
3E
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Binary Address Value, 32-bit Address, bits 15 - 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary Address Value, 32-bit Address, bits 7 - 0
Register Name: RCBADRU
Register Description: Current Receive Buffer Address, upper word
Default Value: x
’
0000
Access: Word Read Only
Intel Hex Address: x
’
3E
Motorola Hex Address: x
’
3C
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Binary Address Value, 32-bit Address, bits 31 - 24
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary Address Value, 32-bit Address, bits 23 - 16