
Programmable Four-Channel Communications Controller
—
CD2481
Datasheet
19
CTS*[0
–
3]
I
CLEAR TO SEND* [0
–
3]:
This input can be programmed to control the flow of transmit data, for
out-of-band flow control applications.
TXCIN
I
TRANSMIT CLOCK:
This pin inputs the transmit clock to the bit rate generator.
CD*
I
CARRIER DETECT*
: This pin is always visible in the MSVR register. CD* is a general purpose
modem input and can be used to cause modem group interrupts upon signal level transitions.
RXCIN
I
RECEIVE CLOCK:
This pin inputs the receive clock to the bit rate generator.
DSR*
I
DATA SET READY*
: This pin is always visible in the MSVR register. DSR* can be used to
validate receive data as well as cause modem group interrupts upon signal level transitions.
TXD[0
–
3]
O
TRANSMIT DATA [0
–
3]:
Serial data output for each channel.
RXD[0
–
3]
I
RECEIVE DATA [0
–
3]:
Serial data input for each channel.
BYTESWAP
I
BYTESWAP:
This pin alters the byte ordering of data during certain 16-bit transfers. It also
changes that half of the data bus on which byte transfers are made, to comply with Intel
or
Motorola
processor systems. BYTESWAP does not alter the bus handshake signals. When
the BYTESWAP pin is high, the byte on A/D[0
–
7] precedes that on A/D[8
–
15] in a string of
transmit or receive bytes. When BYTESWAP is low, A/D[8
–
15] precedes A/D[0
–
7]. When the
BYTESWAP pin is high, bytes are transferred on A/D[0
–
7] when A[0] is low, and on A/D[8
–
15]
when A[0] is high. When BYTESWAP is low, bytes are transferred on A/D[8
–
15] when A[0] is
low, and A/D[0
–
7] when A[0] is high. A different register map is used, depending on the state of
this pin.
Byteswap Byte Alignment
0
Motorola byte alignment
1
Intel byte alignment
Table 1. Pin Descriptions
(Sheet 3 of 3)
Symbol
Type
Description