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參數(shù)資料
| 型號： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁數(shù)： | 48/222頁 |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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CD2481
—
Programmable Four-Channel Communications Controller
48
Datasheet
If there is a non-zero value in the BERCNT (Bus Error Retry Count register), the register is
decremented, and the failed transfer is retried automatically. If the BERCNT is zero, a bus error
interrupt is generated, and DMA transfers are suspended on the failing buffer until the interrupt is
serviced.
5.4.4
A and B Buffers and Chaining
The buffer management of the CD2481 uses a dual-buffer scheme. There is an A and B buffer pair
for each transmitter and each receiver. Each buffer is controlled by an Ownership Status bit, called
2481OWN. When 2481OWN is set to
‘
1
’
, the CD2481 owns the buffer. When 2481OWN is set to
‘
0
’
, the host owns the buffer. A simple rule prevents confusion in the buffer management: neither
the CD2481 nor the host seizes buffer ownership. Each always relinquishes ownership to the other.
The host gives ownership of a receive buffer to the CD2481 when the receive buffer is ready. The
CD2481 is then free to write received data into the buffer. The CD2481 returns ownership of the
receive buffer after the receive data is in the buffer. The host gives ownership of a transmit buffer
to the CD2481 when the transmit buffer is ready to transmit. The CD2481 then transmits the
contents of the buffer. When this is complete, the CD2481 returns ownership back to the host.
The CD2481 keeps track of which buffer (A or B) is to be used next in the status bits
—
Ntbuf for
transmit and Nrbuf for receive. The relationship between the 2481OWN bit and the
‘
next
’
bits is
shown later. The receive buffers are handled in the same way using the Nrbuf (next receive buffer).
Chaining is used to break up relatively long frames into shorter blocks in memory, and is useful
where there are frequent smaller frames and occasional long frames. Chaining allows more
efficient use of the user RAM.
The EOF Status bit is used to control chaining in Synchronous modes. Chaining applies to both
transmit and receive. For transmit, the host determines EOF bit; for receive, the CD2481
determines the EOF bit.
In Transmit DMA, when the first buffer is supplied to the CD2481, it is treated as the start of frame
—
the CRC is reset and leading pad/flag/syn characters are transmitted, followed by the data. If the
EOF bit is set, the CRC and closing flag/syn are appended, and the next buffer is again treated as
the start of frame. If the EOF bit is not set, the CD2481 treats the buffer as the first part of a larger
frame and chains into the next buffer (does not reset CRC); this process then continues until a
buffer is supplied with the EOF bit set.
Table 3. A and B Buffers and Chaining
Ntbuf
2481OWN
Buffer A
2481OWN
Buffer B
Transmit Action
0
0
0
Send nothing
0
1
0
Host sets up buffer A
1
1
0
CD2481 accepts buffer A and marks B as next
1
0
0
CD2481 completes A tx, and passes it to host
1
0
1
Host sets up buffer B
0
0
1
CD2481 accepts B and marks A as next
0
1
1
Host sets up buffer A
1
1
0
CD2481 completes B tx, passes to host, accepts A and marks B as next
1
0
0
CD2481 completes A tx and passes it to host
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