
Programmable Four-Channel Communications Controller
—
CD2481
Datasheet
123
Bit 7
SYN characters
Selects one or two character match for character synchronization to start frame
reception.
0 = SYN1 only (COR6)
1 = SYN1 and SYN2 (COR6 and COR7)
Bit 6
Strip
0 = Do not strip SYN characters from data stream (SYN characters are passed to the
host).
1 = Strip SYN characters from data stream (not passed to the host).
Bit 5:3
Reserved
–
must be zero.
Bit 2
RtsAO
–
RTS automatic output enable
If RtsAO = 1, the RTS* output pin remains active during frame transmission.
Bit 1
CtsAE
–
CTS automatic enable
When clear, the transmitter output enable is independent of the CTS* input pin.
When set, the CTS* input pin is evaluated prior to frame transmission. If CTS* is
asserted low, the frame is transmitted completely. If CTS* is high, frame transmis-
sion is held until CTS* goes low. If CTS* changes after frame transmission begins,
the frame will be transmitted to completion, after which CTS* will once again be
evaluated.
Bit 0
DsrAE
–
DSR automatic enable
When clear, the receiver input enable is independent of the DSR* input pin.
When set, the receiver is enabled only when the DSR* input pin is asserted low. If
DSR* is high, the receiver is disabled until DSR* goes low.
9.2.4
Channel Option Register 3 (COR3)
COR3
–
HDLC Mode
In Synchronous mode, COR3 is used to specify the learning pattern (pad character) sent by the
CD2481 to synchronize the DPLL at the remote end. The pad character (00h or AAh) sent depends
on the kind of encoding used.
Bit 7
Sends pad character(s)
1 = CD2481 sends pad character(s) before sending flag when coming out of the Mark
Idling mode.
0 = CD2481 does not send any pad character.
Register Name: COR3
Register Description: Channel Option Register 3
Default Value: x
’
00
Access: Byte Read/Write
Intel Hex Address: x
’
15
Motorola Hex Address: x
’
16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
sndpad
Alt1
FCSPre
FCS
idle
npad2
npad1
npad0