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參數(shù)資料
| 型號(hào)： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁(yè)數(shù)： | 118/222頁(yè) |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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CD2481
—
Programmable Four-Channel Communications Controller
118
Datasheet
Bit 3
NoStrip
0 = NoStrip disabled; stripping of DLE-SYN or SYN-SYN will occur.
1 = NoStrip enabled; if this bit is set, stripping of DLE-SYN (transparent frames) or
SYN-SYN (non-transparent frames) is disabled. DLE-SYN or SYN-SYN will be
kept in the frame data.
Bit 2
Alternate Control
Alt
–
Ctrl has significance only if COR2 bit 7 (LRC) is 0 (which selects CRC-16), and
COR2 bit 5 is 1, which allows the 7 bit ASCII data in 8 bit EBCDIC format. The
eighth bit is for error-checking, while for transparent case, the host should use CRC
–
16 for error checking. In all cases the CD2481 would use CRC
–
16 calculation and
checking. The burden of checking character validity (through VRC or CRC
–
16 dur-
ing reception) along with 8th bit parity addition (during transmission) is to be burned
by host alone.
Note:
As a side effect, the CRC error bit (set by CD2481) may not be valid for the host. It may be ignored
in case of non-transparent text and may be used in case of transparent text.
Bits 1:0
Extra SYN characters
This field determines the number of extra synchronize (SYN) characters that are
transmitted before a frame is started. The two required SYNs are not included in this
count. This is a binary encode field in which the two required SYNs are followed by
the encoded number of characters (00 = no extra characters; 11 = 3 extra characters)
Note:
In ASCII mode, data is 7 bit with LRC (odd parity) checking only. In EBCDIC mode, data is 8 bit
with CRC checking only. See exception under Alternate Control Bit (COR2 bit 2).
COR2
– A
synchronous
Bit 7
IXM
–
Implied XON mode
IXM has meaning only when TxIBE is set.
If transmission has been stopped due to a received XOFF character, then:
If IXM = 0, then transmission is resumed only after the receipt of an XON character
or a transmit enable command by the Channel Command register (CCR).
If IXM = 1, then transmission is resumed after the receipt of any character or a trans-
mit enable command by the CCR.
Bit 6
TxIBE
–
Transmit in-band flow control enable
If TxIBE is clear, there is no in-band flow control.
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x
’
00
Access: Byte Read/Write
Intel Hex Address: x
’
14
Motorola Hex Address: x
’
17
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IXM
TxIBE
ETC
0
RLM
RtsAO
CtsAE
DsrAE
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