CD2481
—
Programmable Four-Channel Communications Controller
166
Datasheet
Bit 3
Overrun error
–
indicates that new data has arrived, but the CD2481 FIFO or holding
registers are full. The new data is lost, and the overrun indication is flagged on the
last character received before the overrun occurred. In HDLC and Bisync modes, the
remainder of a frame, following an overrun, is discarded.
Bit 2
Residual indication
–
indicates that the last character of the frame was a partial char-
acter.
Bit 1
Reserved
–
returns
‘
0
’
when read.
Bit 0
Clear detect
–
indicates an X.21 data transfer phase clear signal has been detected.
This is defined as two consecutive all-zero receive characters with the CTS* pin
high. Clear Detect mode is enabled by COR1.
Note:
During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the Receive End of Interrupt register. The host can only load one of the two timers in the
interrupt service routine.
RISRl
–
Bisynchronous Mode
Bit 7
Reserved
–
returns
‘
0
’
when read.
Bit 6
EOF
–
End of frame
The EOF bit indicates that a valid End Of Frame has been received, and the frame is
essentially complete.
Bit 5
rxabt
–
Receive abort
The rxabt bit indicates that an abort sequence terminating the frame has been
received.
Bit 4
CRC
–
Receive CRC error
(The terms CRC and FCS are used interchangeably in this document.)
The CRC bit indicates that a frame with a valid end of frame has been received, but
the FCS was not correct.
Bit 3
OE
–
Overrun Error
The OE bit indicates that the receiver buffer and FIFO have been overrun. At least
one new character has been received, but lost since there was no room available in
Register Name: RISRl
Register Description: Receive Interrupt Status Register - Low
Default Value: x
’
00
Access: Byte Read/Write
Intel Hex Address: x
’
8A
Motorola Hex Address: x
’
89
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
EOF
RxAbt
CRC
OE
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary Value for Timer