
CD2481
—
Programmable Four-Channel Communications Controller
20
Datasheet
4.0
Register Summaries
Registers in the CD2481 are either Global or Per-Channel. The column
‘
Address mode
’
in the
memory map on the following pages defines this attribute for each register. Only one set of Global
registers exists, and is accessible by the host at any time. Two sets of Per-Channel registers exist,
and the set accessible at any one time is determined by the currently active channel number. The
channel number is selected by the host in normal (non-interrupt) processing by writing to the
Channel Access register. The channel number in the Channel Access register remains in force until
changed by the host. The channel number is provided automatically by the CD2481 during
interrupt service routines and DMA transfers.
In the following list, some register locations appear twice. They have different names and functions
for asynchronous and synchronous protocol operations. See
Chapter 9.0 on page 112
on of this
datasheet for detailed descriptions of all register functions.
Note also that not all registers are valid at any one time, depending on which functions are included
in the microcode image which has been downloaded. Please refer to end-company dependent
documentation for descriptions of the microcode images.
4.1
Memory Map
4.1.1
Global Registers
The following notes are applicable for
Section 4.1.1
through
Section 4.1.7
.
NOTES:
1. Address mode G: Global register
—
one set is always accessible.
Address mode P: Per-Channel register
—
four sets, one per channel, accessible by CAR or
interrupt context.
2. INT = address for Intel
-style processor.
3. MOT = address for Motorola
-style processor.
Name
Description
Addr.
Mode
1
INT
2
MOT
3
Size
Access
Page
GFRCR
Global Firmware Revision Code Register
G
82
81
B
R/W
112
CAR
Channel Access Register
G
EC
EE
B
R/W
112