
CD2481
—
Programmable Four-Channel Communications Controller
12
Datasheet
1.2
CD2XXX Device Family Compatibility
Features
CD2481
CD2401
CD2431
CD2231
Number of serial channels
4
4
4
2
Interrupt on-chip DMA mechanism
√
1
1.
√
indicates identical operation and register setting.
2.Device microcode is not user-programmable; standard microcode is supplied by Intel.
3.Clock frequency of 60 MHz is required for 230.4 kbps. Applies to Revision B or later CD2481 devices.
4.Clock frequency of 35 MHz is required for 134.4 kbps (CD2401/CD2431); 256 kbps (sync)/230.4 kbps (async) (CD2231).
5.Clock frequency of 35 MHz is required for 134.4 kbps (CD2401/CD2431); 256 kbps (sync)/230.4 kbps (async) (CD2231).
6.Clock frequency of 35 MHz is required for 134.4 kbps (CD2401/CD2431); 256 kbps (sync)/230.4 kbps (async) (CD2231).
7.Compatible with all pins, except those supporting channels 2 and 3 on other family members. These pins are
‘
no connects
’
on
the CD2231 or must be pulled up to V
CC
through a 4.7-k
resistor (see the
CD2481 datasheet
).
√
√
√
FIFO depth (per channel and per direction)
16
16
16
16
Data size (bits)
5-8
5-8
5-8
5-8
Async
Downloaded
2
√
√
√
HDLC/SDLC
Downloaded
√
√
√
X.21, Bisync
Downloaded
√
n/a
n/a
Async-HDLC, PPP (point-to-point protocol)
Downloaded
n/a
√
√
Programmable sync
Downloaded
n/a
n/a
n/a
Serial data rate (kbps)
230.4
3
134.4
4
134.4
5
256/230.4
6
Number of modem leads
(per channel, including RxD and TxD)
10
10
10
10
On-chip timers
√
√
√
√
UNIX
character processing
Downloaded
√
√
√
Special character Tx and recognition
Downloaded
√
√
√
Package
100-pin MQFP
100-pin MQFP
100-pin MQFP
100-pin MQFP
Pin compatibility
CD24X1
CD24X1
CD24X1
CD24X1
7