CD2481
—
Programmable Four-Channel Communications Controller
158
Datasheet
Bit 5
RFram
–
Receive frame status
When set, a frame is being received.
When clear, no frame is being received.
Bit 4
RIdle
–
Receiver idle status
When set, the receiver input is idle.
When clear, the receiver input is not idle.
Note that RFram and RIdle are mutually exclusive.
Bit 3
TxEn
–
Transmitter enabled status
When set, the transmitter is enabled.
When clear, the transmitter is disabled.
Bit 2
Reserved
–
returns
‘
0
’
when read.
Bit 1
TFram
–
Transmit frame status
When set, a frame is being transmitted.
When clear, no frame is being transmitted.
Bit 0
TIdle
–
Transmitter idle status
When set, the transmitter output is idle.
When clear, the transmitter output is not idle.
Note that TFram and TIdle are mutually exclusive.
9.4.4
Modem Signal Value Registers (MSVR)
Modem Signal Value Register (MSVR-RTS)
Modem Signal Value Register (MSVR-DTR)
Register Name: MSVR-RTS
Register Description: Modem Signal Value Register - RTS
Default Value: x
’
00
Access: Byte Read/Write
Intel Hex Address: x
’
DC
Motorola Hex Address: x
’
DE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DSR
CD
CTS
DTRop
0
0
DTR
RTS
Register Name: MSVR-DTR
Register Description: Modem Signal Value Register - DTR
Default Value: x
’
00
Access: Byte Read/Write
Intel Hex Address: x
’
DD
Motorola Hex Address: x
’
DF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DSR
CD
CTS
DTRop
0
0
DTR
RTS