- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379804 > CD2481 (Intel Corp.) Programmable Four-Channel Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁數(shù)： | 18/222頁 |
| 文件大小： | 974K |
| 代理商： | CD2481 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁
CD2481
—
Programmable Four-Channel Communications Controller
18
Datasheet
BERR*
I
BUS ERROR*:
If this input becomes active while the CD2481 is a bus master, the current bus
cycle will be terminated, the bus relinquished, and an interrupt generated to indicate the error to
the host processor.
A[0
–
7]
I/O (TS)
ADDRESS [0
–
7]:
When the CD2481 is not a bus master, these pins are inputs used to
determine which registers are being accessed, or which interrupt is being acknowledged. When
ADLD* is low, A[0
–
7] output address bits 8
–
15 for external latching. When the CD2481 is a bus
master, A[0
–
7] output the least-significant byte of the transfer address.
A/D[0
–
15]
I/O (TS)
ADDRESS/DATA [0
–
15]:
When the CD2481 is not a bus master, these pins provide the 16-bit
data bus for reading and writing to the CD2481 registers. When ADLD* is low, A/D[0
–
15]
provide the upper address bits for external latching. When the CD2481 is a bus master, A/D[0
–
15] provide a multiplexed address/data bus for reading and writing to system memory.
ADLD*
O (TS)
ADDRESS LOAD*:
This is a strobe used to externally latch the upper portion of the system
address bus A[8
–
31]. While ADLD* is low, address bits 16
–
31 are available on A/D[0
–
15], and
address bits 8
–
15 on A[0
–
7].
AEN*
O (TS)
ADDRESS ENABLE*:
This output is used to output enable the external address bus drivers
during CD2481 DMA cycles.
DATEN*
O (TS)
DATA ENABLE*:
This output is active when either the CD2481 is a bus master, or the CS* and
DS* pins are low. It is used to enable the external data bus buffers during host register read/
write operations or during DMA operations. For operations on 32-bit buses, this signal needs to
be gated with A[1] to select the correct half of the data bus.
DATDIR*
O (TS)
DATA DIRECTION*:
This output is active when either the CD2481 is a bus master, or the CS*
pin is low. It is used to control the external data buffers; when low, the buffers should be enabled
in the CD2481 to system bus direction.
CLK
I
CLOCK:
System clock.
BUSCLK
O
BUS CLOCK:
This is the system clock divided by two, which is used internally to control certain
bus operations. This pin is driven low during hardware reset.
RESET*
I
RESET*:
This signal should stay valid for a minimum of 20 ns. The reset state of the CD2481
will be guaranteed at the rising edge of this signal. When RESET* is removed, the CD2481 also
performs a software initialization of its registers.
TEST
I
TEST:
In normal operation, this pin should be kept low. For board-level testing purposes, it
provides a mechanism for forcing normal output pins to High-Impedance mode. When the TEST
pin is high, the following pins will be in High-Impedance mode: BUSCLK, BGOUT*, IACKOUT*,
RXCOUT[0
–
3], RTS*[0
–
3], DTR*[0
–
3], and TXD[0
–
3].
To ensure that all CD2481 outputs are high-impedance, either of the following two conditions
must be met: the RESET* pin can be driven low, and the TEST pin driven high; or the CD2481
is kept in the bus idle state (not accessed for read/write operations nor DMA active), and the
TEST pin is driven high.
RTS*[0
–
3]
O
REQUEST TO SEND* [0
–
3]:
This output can be controlled automatically by the CD2481 to
indicate that data is ready to be sent on the TXD pin.
TXCOUT/DTR*
O
TRANSMIT CLOCK OUT/DATA TERMINAL READY* [0
–
3]:
This output can be controlled
automatically by the CD2481 to indicate that a programmable threshold has been reached in the
receive FIFO. It can also be programmed to output the transmit data clock. Following reset, this
pin will be high and stays high in Clock mode until the transmit channel is enabled for the first
time; after that it remains active independent of the state of the transmit enable. In all modes,
the clock transitions every bit time, even during idle fill in Asynchronous mode. Data transitions
are made on the negative going edge of TXCOUT.
RXCOUT[0
–
3]
O
RECEIVE CLOCK OUT [0
–
3]:
This output provides a one-time bit rate clock for the receive data
in all modes, except when an input (RXCIN) one-time receive clock is used. After reset, this pin
will be low until the channel is receive enabled for the first time, after which it remains active,
independent of the state of receive-enable. When in Asynchronous mode, the output only
transitions while receiving data and not during inter-character fill. The receive data is sampled
on the positive-going edge of this clock.
Table 1. Pin Descriptions
(Sheet 2 of 3)
Symbol
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD3086 | General Purpose NPN Transistor Array |
| CD4000 | CMOS NOR Gates |
| CD4001 | CMOS NOR Gates |
| CD4002 | CMOS NOR Gates |
| CD40011 | Quad 2-Input NOR,NAND Buffered B Series Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD24B3 031573 | 制造商:Comair Rotron 功能描述:FAN 254MM 24VDC |
| CD24B3 | 制造商:Comair Rotron 功能描述:FAN 254MM 24VDC |
| CD-250 | 制造商:Stellar Labs 功能描述:CD / USB Media Player with FM Tuner - MP3 and WMA |
| CD2500R1 | 制造商:LOGETR 功能描述: |
| CD250-3KVM.25 | 制造商:Yageo / Phycomp 功能描述:CD250-3KVM.25 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。