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參數(shù)資料
| 型號： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁數(shù)： | 46/222頁 |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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CD2481
—
Programmable Four-Channel Communications Controller
46
Datasheet
By using the simple and flexible DMA management of the CD2481, the user host processor is
concerned with transmit/receive data on a block-by-block basis. The user does not need to be
concerned with character-by-character transfers, or even filling and emptying the FIFOs. The
DMA control is user-selectable per-channel and operates independently of one another.
The CD2481 can perform DMA operations in any of the supported line protocols. A special
Append mode feature can reduce host CPU overhead for asynchronous data streams. DMA
operations are channel- and direction-specific. In each channel, either the transmitter and the
receiver, or both, can be independently programmed for DMA mode by the CMR (Channel Mode
register).
When the CD2481 acquires the bus for a DMA transfer, only data for one channel and in one
direction is transferred; then, bus ownership is relinquished. A maximum of 16 bytes
—
the depth
of the transmit and receive FIFOs
—
are transferred during any ownership cycle.
Whenever possible, DMA cycles are 16 bits wide, and buffers have the proper byte alignment.
Unaligned buffers are sent using only 8-bit-wide transfers. If the buffer begins on an even address
and contains an odd number of bytes, the CD2481 uses 16-bit transfers for all the words in the
buffer except the last transfer, which is 8 bits.
If one buffer in a chain ends on an odd address, the next buffer in the chain should also start on an
odd address to keep the proper alignment and the most efficient bus usage. In this case, only the
last transfer of the first buffer and the first transfer of the next buffer is 8 bits wide; all others are 16
bits.
The CD2481 can be forced to perform only byte-wide DMA operations by setting the byte DMA
bit in the DMR (DMA Mode register).
5.4.1
Bus Acquisition Cycle
1. CD2481 asserts BR* and waits for BGIN*.
2. When BGIN* is detected, the CD2481 can access the bus after the current bus owner
relinquishes control of the bus.
3. If BGACK* is high when BGIN* goes low, then the bus is free to access. In this case, go to
step 5.
4. If BGACK* is low when BGIN* goes low, then the bus is in use. The CD2481 waits for
BGACK* to go high.
5. Once the CD2481 senses that BGACK* is high, it waits for the current bus cycle to terminate
(DS* and DTACK* high) and then asserts BGACK* by driving it low. At that time, the
CD2481
‘
owns
’
the bus. After driving BGACK* low, the CD2481 drives BR* high.
Figure 5 on page 47
is an example in which the CD2481 was required to wait to access the bus.
5.4.2
DMA Data Transfer
After the CD2481 acquires the bus, it pulses ADLD* once. This loads the upper 24 address bits to
the external 24-bit latch. This happens only once per DMA grant cycle. The AD[0
–
15] bits are
remapped to Memory Address bits MA[16
–
31], and A[0
–
7] are mapped to MA[8
–
15]. If during
DMA, the upper 24 bits need to change, the CD2481 relinquishes the bus and then reacquires the
bus.
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