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參數資料
| 型號： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁數： | 49/222頁 |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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Programmable Four-Channel Communications Controller
—
CD2481
Datasheet
49
5.4.5
Transmit DMA Transfer
As in receive data transfers, two buffers are available for DMA transmit transfers. The ATBADR/
BTBADR and ATBCNT/ BTBCNT (Transmit Buffer Address and Transmit Buffer Count
registers) contain the start address of and the byte count in the buffers. These registers are set by the
host when initiating a transfer. The CD2481 makes a copy of the registers to perform the transfer,
leaving the originals unchanged. Transfer of buffers between the host and the CD2481 is controlled
by the ATBSTS/BTBSTS (Transmit Buffer Status) registers.
Buffers can contain either complete frames or blocks of data, linked together to form a complete
frame or a block, or used in an Append mode to transmit data as it arrives from another process.
The first two transfer types are Block mode transfers, the last is the Append mode, and both are
described below. The management of the buffers reduces the processor overhead associated with
short data transfers and increases the minimum response time requirements for frame-based
transmissions.
Chain Mode Transfer
In this mode, the frame should be complete in buffers in memory before transmission is started.
The Append Status bit should not be set; the Start of Frame bit must be set to begin transmission,
and the Last Buffer bit must be set if this buffer is the last in a chained block or is a complete frame
or a block.
When the CRC bit is set, the CD2481 generates and transmits a cyclic redundancy check word for
the frame using the polynomial selected by the CPSR (CRC Polynomial Select register). A host
interrupt is generated after the buffer is transmitted, if the Interrupt Required bit is set.
Transmit buffers can be chained to support large frames. To minimize bus usage, the first buffer of
the chain should begin on an even address in host memory. The CD2481 begins fetching a frame
from a buffer performing DMA transfer, reading two bytes at a time. The CD2481 cannot realign
data between external memory and the FIFO. If one buffer of the chain ends on an odd address, the
next buffer in the chain should begin on an odd address. Otherwise, only single-byte transfers are
made for the rest of the buffer.
Append Mode Transfer
This mode is available for buffer A in Asynchronous mode only. If buffer A is set to Append mode,
the host can enable the CD2481 to transmit data in the buffer before it is completely filled. The
CD2481 starts transmitting new data when it is appended to the buffer.
This mode is useful for terminal echo routines that do not wait for a complete block to be formed
before starting transmission. In this mode, transmission is started when the buffer is made available
to the CD2481 by the host; the ATBADR[0
–
3] and the ATBCNT[L, H] are initialized. Subsequent
triggering of DMA transfer occurs by programming the ATBCNT[L, H] with the accumulated byte
count. The ATBCNT should be written as a 16-bit word in this case, to avoid confusion between 2-
byte operations. The ATBADR[0
–
3] should not be reprogrammed during the Append mode. If the
memory space has to be moved, the Append mode has to be disabled first. When the final data is
added to the append buffer and ATBCNT has been updated, the host should set the AppdCmp bit in
STCR. When the CD2481 has completed the final transmission, it clears the 2481OWN bit in the
ATBSTS register, and generate an end-of-buffer interrupt. Only the A buffer can be used in the
Append mode.
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