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參數(shù)資料
| 型號： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁數(shù)： | 52/222頁 |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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CD2481
—
Programmable Four-Channel Communications Controller
52
Datasheet
13. By this time, the host has set up a new buffer for buffer B. The EOF bit in the BTBSTS is set
to indicate that this is the last link in the chain.
14. The CD2481 then transmits buffer B in the same manner shown above. As before, the CD2481
transmits the number of bytes indicated in the BTBCNT, which is 40 for the third segment.
15. When the CD2481 completes transmission, any necessary CRCs and ending frame delimiters
are transmitted.
16. The CD2481 optionally interrupts the host with EOF and EOB set in the TISR to indicate that
the transmission is complete, and this is the last link in the chain.
5.4.7
Receive DMA Transfer
In all protocol modes, two host memory buffers can be made available to each receive channel, by
the ARBADR/BRBADR and ARBCNT/BRBCNT (Receive Buffer Address and Receive Buffer
Count registers). To make a buffer available, the user must supply the buffer address in the Receive
Buffer Address registers; the number of free bytes in the buffer must be written in the Receive
Buffer Count registers, and the buffer status must be updated in ARBSTS/BRBSTS (Receive
Buffer Status register). The CD2481 is then free to use the buffer for receive data, and update the
Buffer Status register as appropriate. When the buffer is no longer in use, the CD2481 writes the
number of bytes stored in the buffer in RBCNT and updates status in RBSTS. This frees the host to
take control of this buffer and supply a new buffer in its place. The CD2481 automatically switches
to the other buffer whenever one buffer becomes full, or the end of a frame has been reached. If the
other buffer has not been allocated, the host still has the time required to fill the CD2481 16-byte
FIFO in which to respond and avoid loss of data.
Special actions are taken depending on the channel protocol. In HDLC mode, the end-of-frame/
data block boundaries are recognized by the CD2481. When a data-block boundary is detected, the
current buffer is automatically terminated. If the other buffer is allocated and owned by the
CD2481, it becomes the current buffer. End-of-frame and block interrupts are also generated to the
host.
In Asynchronous mode, a host interrupt is generated when there are receive exceptions (framing
error, special character, and so on), but the buffer is not terminated. The data and exception status
are made available to the host, just as when the Asynchronous mode is purely interrupt-driven.
New data is buffered internally in the FIFO until the host services the exception interrupt. The host
has the following three options when terminating an exception interrupt:
1. The exception character can be discarded.
2. The buffer can be terminated, if it is then no additional interrupt would be generated. The
transfer count is not provided in A/BRBCNT, but can be calculated by RCBADR (Receive
Current Buffer Address).
3. A user-defined gap can be left in the buffer.
These selections are communicated to the CD2481 by the value written by the host to the Receive
End of Interrupt register, when the Receive Interrupt service is completed. Leaving an
‘
n
’
byte gap
enables the host to insert status of its own in the current buffer, while continuing to receive data in
the same buffer. This eliminates the overhead of allocating a new buffer. The host must have noted
the starting location of the gap while in the exception interrupt. This is done by reading the Receive
Current Buffer Address register. The address in this register is guaranteed to be stable during the
Receive Interrupt, and to point to the next free character location in the current DMA buffer. If the
size of the gap supplied by the host is sufficient to fill or complete the current buffer, the CD2481
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