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參數(shù)資料
| 型號(hào)： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁數(shù)： | 55/222頁 |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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Programmable Four-Channel Communications Controller
—
CD2481
Datasheet
55
14. In this example, the third link does not fill the buffer. Thus, when the end of frame delimiter is
detected by the CD2481, the value of 40 (for 40 received bytes) is written into the received
byte count
—
BRBCNT.
15. Next, the CD2481 sets the EOB and EOF bits to show that the buffer is complete, and that this
is the last link in the chain.
16. The CD2481 optionally interrupts the host with EOF and EOB set in the RISR to indicate that
the received frame is complete, and this was the last link in the chain.
5.4.7.1
Buffer Allocation
The CD2481 contains two DMA descriptors that can be loaded by the CPU to specify transmit
buffers. These descriptors are designated A and B, and each consists of a 32-bit address (A/
BTBADR), a 16-bit count (A/BTBCNT), and an 8-bit status (A/BTBSTS).
The Status register contains an Ownership Status bit
—
2481OWN. When this bit is set, the
CD2481 owns the descriptor, and it should not be written to by the CPU. When the bit is clear, the
descriptor is owned by the CPU.
When DMA is selected and the channel is enabled, the CD2481 waits for ownership of buffer A.
When ownership of A is given by setting the 2481OWN bit, the buffer is transmitted, and then the
ownership bit is cleared. The CD2481 waits for ownership of buffer B; this process continues,
toggling between the two buffer descriptors.
The DMABSTS register contains a status bit (NtBuf) that informs the CPU of the next buffer to
transmit to ensure that the CPU and CD2481 stay in synchronization. This procedure ensures that a
pipeline of data is available for the CD2481 to send, maximizing the bandwidth utilization and
minimizing the possibility of underruns.
Figure 9
on the following page illustrates this procedure.
5.4.7.2
Interrupts for Transmit DMA Buffers
Two types of transmit interrupts are available in DMA mode; they are enabled by the Interrupt
Enable register (IER) and controlled by the TxD and TxMpty bits.
When the TxMpty interrupt is enabled, interrupts are generated when there is no transmit data
available to send. For example, the TxMpty interrupt can be used by the CPU to determine when
line turnaround can occur on half-duplex lines.
Normally, the TxDat interrupt is used to indicate the end of each transmit buffer. The interrupt is
scheduled internally when the last data is read from the transmit buffer into the FIFO.
Because only one interrupt is generated for each buffer, the TxD bit in the IER register can be left
permanently enabled. If interrupts are required selectively for individual buffers, the INTR bit in
the A/BTBSTS registers can be used to selectively enable interrupts.
5.4.7.3
Chained Buffers
In Synchronous modes, when the frame size exceeds the maximum buffer size, a frame can be
transmitted from a number of separate buffers. This is achieved simply by not setting the EOF bit
in the A/BTBSTS (Transmit Buffer Status register) until the last buffer of the frame. The CD2481
transmits the buffers as one frame; it appends the CRC only when all the data is transmitted from
the buffer with the EOF flag set.
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