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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 81/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
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Data Book
81
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Timing Parameters
Table 23
Timing Parameter Summary
Parameter Description
Min
-40
-800
Min
-45
-800
Min
-45
-711
Min
-53
-600
Max
Unit
Figure
t
RC
Row Cycle time of RDRAM banks - the
interval between ROWA packets with ACT
commands to the same bank.
28
28
28
28
–
t
CYCLE
Figure 15
Figure 16
t
RAS
RAS-asserted time of RDRAM bank - the
interval between ROWA packet with ACT
command and next ROWR packet with
PRER
command to the same bank.
20
20
20
20
64
μ
s
2)
t
CYCLE
Figure 15
Figure 16
t
RP
Row Precharge time of RDRAM banks -
the interval between ROWR packet with
PRER
a
command and next ROWA packet
with ACT command to the same bank.
8
8
8
8
–
t
CYCLE
Figure 15
Figure 16
t
PP
Precharge-to-precharge time of RDRAM
device - the interval between successive
ROWR packets with PRER
commands to
any banks of the same device.
8
8
8
8
–
t
CYCLE
Figure 12
t
RR
RAS-to-RAS time of RDRAM device - the
interval between successive ROWA
packets with ACT commands to any
banks of the same device.
8
8
8
8
–
t
CYCLE
Figure 13
t
RCD
RAS-to-CAS Delay - the interval from
ROWA packet with ACT command to
COLC packet with RD or WR command).
Note - the RAS-to-CAS delay seen by the
RDRAM core (
t
) is equal to
t
= 1
+
t
because of differences in the row
and column paths through the RDRAM
interface.
7
9
7
7
–
t
CYCLE
Figure 15
Figure 16
t
CAC
CAS Access delay - the interval from RD
command to Q read data. The equation for
t
is given in the TPARM register in
Figure 39
.
8
8
8
8
12
t
CYCLE
Figure 4
Figure 39
t
CWD
CAS Write Delay (interval from WR
command to D write data.
6
6
6
6
6
t
CYCLE
Figure 4
t
CC
CAS-to-CAS time of RDRAM bank - the
interval between successive COLC
commands).
4
4
4
4
-
t
CYCLE
Figure 15
Figure 16
t
PACKET
Length of ROWA, ROWR, COLC, COLM
or COLX packet.
4
4
4
4
4
t
CYCLE
Figure 3
t
RTR
Interval from COLC packet with WR
command to COLC packet which causes
retire, and to COLM packet with
bytemask.
8
8
8
8
-
t
CYCLE
Figure 17
t
OFFP
The interval (offset) from COLC packet
with RDA command, or from COLC packet
with retire command (after WRA automatic
precharge), or from COLC packet with
PREC command, or from COLX packet
with PREX command to the equivalent
ROWR packet with PRER. The equation
for
t
is given in the TPARM register in
Figure 39
.
4
4
4
4
4
t
CYCLE
Figure 14
Figure 39
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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