- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370785 > HYB25M128160C (SIEMENS AG) 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) PDF資料下載
參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 62/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁當前第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
62
2.00
Figure 46
STBY Entry (left) and STBY Exit (right)
Figure 47
NAP Entry (left) and PDN Entry (right)
On the right side of
Figure 48
, an RDRAM exits PDN state at the end of cycle T
3
. This RDRAM may
not re-enter PDN or NAP state for an interval of
t
PU0
. The RDRAM enters PDN state at the end of
cycle T
13
. This RDRAM may not re-exit PDN state for an interval of
t
PU1
. The equations for these two
parameters depend upon a number of factors, and are shown at the bottom of the figure. PDNX is
the value in the PDNX field in the PDNX register.
at (TFRM)
or later.
ATTN
Power
State
t
AS
STBY
State
DQB8...0
DQA8...0
Power
t
CYCLE
SPT04232
at (TFRM - 4)*
device (d1!= d0) is okay
STBY
ATTN
SA
t
or earlier.
t
*
CYCLE
ROP a0
CTM/CFM
ROW2...
ROW0
COL4...
COL0
DQB8...0
DQA8...0
RLXX
RLXC
RLXR
T0
T3
T1
T2
T4
T5
COL4...
COL0
ROW2...
ROW0
CTM/CFM
T8
T6
T7
T9
T10
T13
T11 T12
T14
T0
T1
T2
A COL packet to device d0
(or any other device) is okay
a1 = {d1, b1, c1}
ROWA or ROWR/ATTN
a0 = {d0, b0, r0}
ROP = non-broadcast
No COL packets may be
placed in the three
indicated positions; i.e. at
(TFRM - {1, 2, 3})
COP a0
XOP a0
TFRM
COP a1
XOP a1
*
t
CYCLE
T5
T4
T3
T6
T7
T10
T9
T8
T11 T12
T15
T14
T13
T16
CYCLE
t
*
owerlap the restricted
interval
The (eventual) NAP / PDN exit will be to the same ATTN / STBY state the RDRAM was in prior to NAP / PDN entry
Power
State
a)
DQA8...0
DQB8...0
NAP
a)
ATTN / STBY
ASN
t
State
Power
DQA8...0
DQB8...0
SPT04233
the restricted interval will
be ignored
directed to device d0 after
ROW or COL packets
ATTN / STBY
a)
ASP
t
PDN
ROP a0
(NAPR)
COP a0
XOP a0
COL0
COL4...
ROW0
ROW2...
CTM/CFM
T0
T1
T2
T3
Restricted
ROP a1
Restricted
NPQ
t
XOP a1
COP a1
t
CD
COL0
COL4...
ROW0
CTM/CFM
ROW2...
T6
T5
T4
T7
T8
T11
T10
T9
T12 T13 T14
T0
No ROW or COL packets
directed to device d0 may
overlap the restricted
interval. No broadcast
ROW packets may overlap
the quiet interval
device other than d0 may
ROW or COL packets to a
a1 = {d1, b1,r1, c1}
a0 = {d0, b0, r0, c0}
COP a1
XOP a1
ROP a1
Restricted
(PDNR)
Restricted
XOP a0
COP a0
NPQ
t
ROP a0
CD
t
T3
T1
T2
T4
T5
T8
T6
T7
T9
T10
T13
T11 T12
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
發(fā)布緊急采購，3分鐘左右您將得到回復。