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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 43/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
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Data Book
43
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Initialization
Figure 26
SIO Reset Sequence
Initialization refers to the process that a controller must go through after power is applied to the
system or the system is reset. The controller prepares the RDRAM sub-system for normal Channel
operation by (primarily) using a sequence of control register transactions on the serial CMOS pins.
The following steps outline the sequence seen by the various memory subsystem components
(including the RDRAM components) during initialization. This sequence is available in the form of
reference code. Contact Rambus Inc. for more information.
1. Start Clocks
– This step calculates the proper clock frequencies for PClk (controller logic),
SynClk (RAC block), RefClk (DRCG component), CTM (RDRAM component), and SCK (SIO
block).
2. RAC Initialization
– This step causes the INIT block to generate a sequence of pulses which
resets the RAC, performs RAC maintenance operations, and measures timing intervals in order
to ensure clock stability.
3. RDRAM Initialization
– This stage performs most of the steps needed to initialize the RDRAMs.
The rest are performed in stages 5.0, 6.0, and 7.0. All of the steps in 3.0 are carried out through
the SIO block interface.
3.1./3.2. SIO Reset
– This reset operation is performed before any SIO control register read or
write transactions. It clears six registers (TEST34, CCA, CCB, SKIP, TEST78, and
TEST79) and places the INIT register into a special state (all bits cleared except SKP and
SDEVID fields are set to ones).
3.3. Write TEST77 Register
– The TEST77 register must be explicitly written with zeros before
any other registers are read or written.
3.4. Write TCYCLE Register
– The TCYCLE register is written with the cycle time
t
CYCLE
of the
CTM clock (for Channel and RDRAMs) in units of 64ps. The
t
CYCLE
value is determined in
stage 1.0.
3.5. Write SDEVID Register
– The SDEVID (serial device identification) register of each
RDRAM is written with a unique address value so that directed SIO read and write
transactions can be performed. This address value increases from 0 to 31 according to the
distance an RDRAM is from the ASIC component on the SIO bus (the closest RDRAM is
address 0).
SPT04230
from SIO0 to SIO1
The packet is repeated
SIO1
0000000000000000
1
0
0
00001100
SIO0
CMD
SCK
T0
00000000...00000000
0000000000000000
1
1
0
0
T16
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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