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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 34/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
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Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
34
2.00
Figure 18
(left) shows the result of performing a RD command to the same device in the same
COLC packet slot that would normally be used for the retire operation. The read may be to any bank
and column address; all that matters is that it is to the same device as the WR command. The retire
operation and MSK(a1) will be delayed by a time
t
PACKET
as a result. If the RD command used the
same bank and column address as the WR command, the old data from the sense amp would be
returned. If many RD commands to the same device were issued instead of the single one that is
shown, then the retire operation would be held off an arbitrarily long time. However, once a RD to
another device or a WR or NOCOP to any device is issued, the retire will take place.
Figure 18
(right) illustrates a situation in which the controller wants to issue a WR-WR-RD COLC packet
sequence, with all commands addressed to the same device, but addressed to any combination of
banks and columns.
The RD will prevent a retire of the first WR from automatically happening. But the first dualoct D(a1)
in the write buffer will be overwritten by the second WR dualoct D(b1) if the RD command is issued
in the third COLC packet. Therefore, it is required in this situation that the controller issue a NOCOP
command in the third COLC packet, delaying the RD command by a time of
t
PACKET
. This situation
is explicitly shown in
Table 13
for the cases in which
t
CCDELAY
is equal to
t
RTR
.
Figure 18
Retire Held Off by Read (left) and Controller Forces WWR Gap (right)
Figure 19
shows a possible result when a retire is held off for a long time (an extended version of
Figure 18
-left). After a WR command, a series of six RD commands are issued to the same device
(but to any combination of bank and column addresses). In the meantime, the bank Ba to which the
WR command was originally directed is precharged, and a different row Rc is activated. When the
retire is automatically performed, it is made to this new row, since the write buffer only contains the
bank and column address, not the row address. The controller can insure that this doesn’t happen
by never precharging a bank with an unretired write buffer. Note that in a system with more than one
RDRAM, there will never be more than two RDRAMs with unretired write buffers. This is because
DQB8...0
DQA8...0
t
Transaction a: WR
Transaction b: RD
DQA8...0
DQB8...0
a1 = {Da, Ba, Ca1}
b1 = {Da, Bb, Cb1}
PACKET
RTR
CWD
t
+
t
D (a1)
Q
c1 = {Da, Bc, Cc1}
b1 = {Da, Bb, Cb1}
a1 = {Da, Ba, Ca1}
t
CWD
Transaction c: RD
Transaction b: WR
Transaction a: WR
t
D (a1)
RTR
D (b1)
SPA04222
ROW2...
ROW0
CTM/CFM
COL4...
COL0
T5
The retire operation for a write can be
held off by a read to the same device
CTM/CFM
COL0
ROW2...
ROW0
COL4...
WR a1
T0
T1
T2
T4
T3
CAC
retire (a1)
MSK (a1)
RD b1
t
T15
T10
T6
T7
T9
T8
T11 T12
T14
T13
T20
T16 T17
T19
T18
The controller must insert a NOCOP to retire (a1)
to make room for the data (b1) in the write buffer
WR a1
WR b1
retire (a1)
MSK (a1)
RD c1
T0
T1
T3
T2
T4
T5
T6
T9
T8
T7
T10 T11
T14
T13
T12
T15 T16
CAC
t
T19
T18
T17
T20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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