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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 75/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
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Data Book
75
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
RSL - Transmit Timing
Figure 55
is a timing diagram which shows the detailed requirements for the RSL output signals on
the Channel.
The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on
the Channel. Each signal is driven twice per
t
CYCLE
interval. The beginning and end of the even
transmit window is at the 75% point of the previous cycle and at the 25% point of the current cycle.
The beginning and end of the odd transmit window is at the 25% point and at the 75% point of the
current cycle. These transmit points are measured relative to the crossing points of the falling CTM
clock edge. The size of the actual transmit window is less than the ideal
t
CYCLE
/2, as indicated by the
non-zero values of
t
Q,MIN
and
t
Q,MAX
. The
t
Q
parameters are measured at the 50% voltage point of the
output transition.
The
t
QR
and
t
QF
rise- and fall-time parameters are measured at the 20% and 80% points of the
output transition.
Figure 55
RSL Timing - Data Signals for Transmit
CMOS - Receive Timing
Figure 56
is a timing diagram which shows the detailed requirements for the CMOS input signals.
The CMD and SIO0 signals are inputs which receive information transmitted by a controller (or by
another RDRAM’s SIO1 output. SCK is the CMOS clock signal driven by the controller. All signals
are high true.
SPT04241
20%
V
QL
QH
50%
80%
V
DQB
QR
t
t
Q, MAX
CTM
80%
50%
CIH
CIL
20%
V
V
CTMN
X-
V
X+
V
V
CM
DQA
t
QF
t
CYCLE
Q, MAX
t
0.25 x
0.75 x
CYCLE
t
Q, MIN
t
t
Q, MIN
CYCLE
0.75 x
t
Odd
Even
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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