參數(shù)資料
型號(hào)： HYB25M128160C
廠商： SIEMENS AG
英文描述： 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM)
中文描述： 128 - Mbit的直接的RDRAM（128兆直接的RDRAM）
文件頁(yè)數(shù)： 61/93頁(yè)
文件大小： 919K
代理商： HYB25M128160C
Data Book
61
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Figure 47
shows the NAP entry sequence (left). NAP state is entered by sending a NAPR
command in a ROW packet. A time
t
ASN
is required to enter NAP state (this specification is provided
for power calculation purposes). The clock on CTM/CFM must remain stable for a time
t
CD
after the
NAPR command.
The RDRAM may be in ATTN or STBY state when the NAPR command is issued. When NAP state
is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state
and a RLXR command is specified with NAPR, then the RDRAM will return to STBY state when
NAP is exited.
Figure 47
also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR
command in a ROW packet. A time
t
ASP
is required to enter PDN state (this specification is provided
for power calculation purposes). The clock on CTM/CFM must remain stable for a time
t
CD
after the
PDNR command.
The RDRAM may be in ATTN or STBY state when the PDNR command is issued. When PDN state
is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state
and a RLXR command is specified with PDNR, then the RDRAM will return to STBY state when
PDN is exited. The current- and slew-rate-control levels are re-established.
The RDRAM’s write buffer must be retired with the appropriate COP command before NAP or PDN
are entered. Also, all the RDRAM’s banks must be precharged before NAP or PDN are entered. The
exception to this is if NAP is entered with the NSR bit of the INIT register cleared (disabling
self-refresh in NAP). The commands for relaxing, retiring, and precharging may be given to the
RDRAM as late as the ROPa0, COPa0, and XOPa0 packets in
Figure 47
. No broadcast packets
nor packets directed to the RDRAM entering Nap or PDN may overlay the quiet window. This
window extends for a time
t
NPQ
after the packet with the NAPR or PDNR command.
Figure 48
shows the NAP and PDN exit sequences. These sequences are virtually identical; the
minor differences will be highlighted in the following description.
Before NAP or PDN exit, the CTM/CFM clock must be stable for a time
t
CE
. Then, on a falling and
rising edge of SCK, if there is a “01” on the CMD input, NAP or PDN state will be exited. Also, on the
falling SCK edge the SIO0 input must be at a 0 for NAP exit and 1 for PDN exit.
If the PSX bit of the INIT register is 0, then a device PDEV5 … 0 is specified for NAP or PDN exit
on the DQA5 … 0 pins. This value is driven on the rising SCK edge 0.5 or 1.5 SCK cycles after the
original falling edge, depending upon the value of the DQS bit of the NAPX register. If the PSX bit
of the INIT register is 1, then the RDRAM ignores the PDEV5 … 0 address packet and exits NAP or
PDN when the wake-up sequence is presented on the CMD wire. The ROW and COL pins must be
quiet at a time
t
S4
/
t
H4
around the indicated falling SCK edge (timed with the PDNX or NAPX register
fields). After that, ROW and COL packets may be directed to the RDRAM which is now in ATTN or
STBY state.
Figure 49
shows the constraints for entering and exiting NAP and PDN states. On the left side, an
RDRAM exits NAP state at the end of cycle T
3
. This RDRAM may not re-enter NAP or PDN state
for an interval of
t
NU0
. The RDRAM enters NAP state at the end of cycle T
13
. This RDRAM may not
re-exit NAP state for an interval of
t
NU1
. The equations for these two parameters depend upon a
number of factors, and are shown at the bottom of the figure. NAPX is the value in the NAPX field
in the NAPX register.
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