參數(shù)資料
型號(hào)： HYB25M128160C
廠商： SIEMENS AG
英文描述： 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM)
中文描述： 128 - Mbit的直接的RDRAM（128兆直接的RDRAM）
文件頁(yè)數(shù)： 27/93頁(yè)
文件大?。?/td> 919K
代理商： HYB25M128160C
Data Book
27
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
performed, this interval must be increased). The precharge operation requires the interval
t
RP,MIN
to
complete.
Adjacent Banks:
An RDRAM with a “s” designation (256K
×
32s
×
16/18) indicates it contains “split
banks”. This means the sense amps are shared between two adjacent banks. The only exception
is that sense amp 0, 15, 30, and 31 are not shared. When a row in a bank is activated, the two
adjacent sense amps are connected to (associated with) that bank and are not available for use by
the two adjacent banks. These two adjacent banks must remain precharged while the selected bank
goes through its activate, restore, read/write, and precharge operations.
For example (referring to the block diagram of
Figure 2
), if bank 5 is accessed, sense amp 4/5 and
sense amp 5/6 will both be loaded with one of the 512 rows (with 512 bytes loaded into each sense
amp from the 1 Kbyte row - 256 bytes to the DQA side and 256 bytes to the DQB side). While this
row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense
amp sharing.
Precharge Mechanisms
Figure 13
shows an example of precharge with the ROWR packet mechanism. The PRER
command must occur a time
t
RAS
after the ACT command, and a time
t
RP
before the next ACT
command. This timing will serve as a baseline against which the other precharge mechanisms can
be compared.
Figure 13
Precharge via PRER Command in ROWR Packet
Figure 14
(top) shows an example of precharge with a RDA command. A bank is activated with an
ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in
COLC packets on the COL pins. The fourth of these commands is a RDA, which causes the bank
to automatically precharge when the final read has finished. The timing of this automatic precharge
is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time
t
OFFP
SPA04217
T24
ROW2...
ROW0
COL4...COL0
DQB8...0
DQA8...0
RP
t
CTM/CFM
T2
T1
T0
T3
T4
T14
T7
T5
T6
T8
T9
T12
T10 T11
T13
T19
T17
T15 T16
T18
T20 T21
T23
T22
T44
T34
T29
T25 T26
T28
T27
T30 T31
T33
T32
T39
T35 T36 T37 T38
T40 T41 T42 T43
T46
T45
T47
ACT a0
ACT b0
PRER a5
RAS
t
t
RC
a0 = {Da, Ba, Ra}
a5 = {Da, Ba}
b0 = {Da, Ba, Rb}
相關(guān)PDF資料
PDF描述
HYB25R128160C 128-MBit Direct RDRAM(128 M位直接RDRAM)
HYB 25M144180C 144-MBit Direct RDRAM(144 M位直接RDRAM)
HYB25R144180C 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
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HYB3116160BSJ-60 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BSJ-70 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BST-50 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
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