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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 44/93頁 |
| 文件大小： | 919K |
| 代理商： | HYB25M128160C |
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Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
44
2.00
3.6. Write DEVID Register
– The DEVID (device identification) register of each RDRAM is
written with a unique address value so that directed memory read and write transactions
can be performed. This address value increases from 0 to 31. The DEVID value is not
necessarily the same as the SDEVID value. RDRAMs are sorted into regions of the same
core configuration (number of bank, row, and column address bits and core type).
3.7. Write PDNX,PDNXA Registers
– The PDNX and PDNXA registers are written with values
that are used to measure the timing intervals connected with an exit from the PDN
(powerdown) power state.
3.8. Write NAPX Register
– The NAPX register is written with values that are used to measure
the timing intervals connected with an exit from the NAP power state.
3.9. Write TPARM Register
– The TPARM register is written with values which determine the
time interval between a COL packet with a memory read command and the Q packet with
the read data on the Channel. The values written set each RDRAM to the minimum value
permitted for the system. This will be adjusted later in stage 6.0.
3.10. Write TCDLY1 Register
– The TCDLY1 register is written with values which determine the
time interval between a COL packet with a memory read command and the Q packet with
the read data on the Channel. The values written set each RDRAM to the minimum value
permitted for the system. This will be adjusted later in stage 6.0.
3.11. Write TFRM Register
– The TFRM register is written with a value that is related to the
t
RCD
parameter for the system. The
t
RCD
parameter is the time interval between a ROW packet
with an activate command and the COL packet with a read or write command.
3.12. 3.12 SETR/CLRR
– Each RDRAM is given a SETR command and a CLRR command
through the SIO block. This sequence performs a second reset operation on the RDRAMs.
3.13. Write CCA and CCB Registers
- These registers are written with a value halfway between
their minimum and maximum values. This shortens the time needed for the RDRAMs to
reach their steady-state current control values in stage 5.0.
3.14. Powerdown Exit
– The RDRAMs are in the PDN power state at this point. A broadcast
PDNExit command is performed by the SIO block to place the RDRAMs in the RLX (relax)
power state in which they are ready to receive ROW packets.
3.15. SETF
- Each RDRAM is given a SETF command through the SIO block. One of the
operations performed by this step is to generate a value for the AS (autoskip) bit in the SKIP
register and fix the RDRAM to a particular read domain.
4. Controller Configuration
– This stage initializes the controller block. Each step of this stage will
set a field of the ConfigRMC[63:0] bus to the appropriate value. Other controller implementations
will have similar initialization requirements, and this stage may be used as a guide.
4.1. Initial Read Data Offset
– The ConfigRMC bus is written with a value which determines
the time interval between a COL packet with a memory read command and the Q packet
with the read data on the Channel. The value written sets RMC.d1 to the minimum value
permitted for the system. This will be adjusted later in stage 6.0.
4.2. Configure Row/Column Timing
– This step determines the values of the
t
RAS,MIN
,
t
RP,MIN
,
t
RC,MIN
,
t
RCD,MIN
,
t
RR,MIN
, and
t
PP,MIN
RDRAM timing parameters that are present in the
system. The ConfigRMC bus is written with values that will be compatible with all RDRAM
devices that are present.
4.3. Set Refresh Interval
– This step determines the values of the
t
REF,MAX
RDRAM timing
parameter that are present in the system. The ConfigRMC bus is written with a value that
will be compatible with all RDRAM devices that are present.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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