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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 19/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
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Data Book
19
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
ROW-to-COL Packet Interaction
Figure 7
shows two packets on the ROW and COL pins. They must be separated by an interval
t
RCDELAY
which depends upon the packet contents.
Table 12
summarizes the
t
RCDELAY
values for all
possible cases. Note that if the COL packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.
Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command.
Figure 15
and
Figure 16
show examples of RC5 - an activation followed by a read or write. RC4 is
an illegal situation, since a read or write of a precharged banks is being attempted (remember that
for a bank to be activated, adjacent banks must be precharged). In cases RC1, RC2, and RC3,
there is no interaction of the ROW and COL packets.
Figure 7
ROW-to-COL Packet Interaction - Timing
Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There
is either no interaction (RC6 through RC9) or an illegal situation with a read or write of a precharged
bank (RC9).
The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in
a COLC packet or a PREX command in a COLX packet. The constraints of these precharge
operations may be converted to equivalent PRER command constraints using the rules
summarized in
Figure 14
.
Transaction b: COPb
Transaction a: ROPa
DQB8...0
DQA8...0
b1 = {Db, Bb, Cb1}
a0 = {Da, Ba, Ra}
SPT04211
COL4...COL0
ROW2...
ROW0
CTM/CFM
COPb b1
T0
T1
T3
T2
T4
T17
T11
ROPa a0
T8
RCDELAY
t
T5
T6
T7
T9 T10
T14
T12 T13
T15 T16
T18 T19
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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