參數(shù)資料
型號： HYB25M128160C
廠商： SIEMENS AG
英文描述： 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM)
中文描述： 128 - Mbit的直接的RDRAM（128兆直接的RDRAM）
文件頁數(shù)： 7/93頁
文件大?。?/td> 919K
代理商： HYB25M128160C
Data Book
7
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
RD Command
: The RD (read) command causes one of the 64 dualocts of one of the sense amps
to be transmitted on the DQA/DQB pins of the Channel.
WR Command
: The WR (write) command causes a dualoct received from the DQA/DQB data pins
of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC
bank address and C column address information. The data in the write buffer is automatically retired
(written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a
subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device,
or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the
same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turn-
around.
PREC Precharge
: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR,
except that a precharge operation is performed at the end of the column operation. These
commands provide a second mechanism for performing precharge.
PREX Precharge
: After a RD command, or after a WR command with no byte masking (M = 0), a
COLX packet may be used to specify an extended operation (XOP). The most important XOP
command is PREX. This command provides a third mechanism for performing precharge.
Packet Format
Figure 3
shows the formats of the ROWA and ROWR packets on the ROW pins.
Table 5
describes
the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4
device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by
the RDRAM.
The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the
ROWA and ROWR packet provide a five bit device address and a five bit bank address. An ROWA
packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the
remaining bits for an eleven bit opcode field. Note the use of the “RsvX” notation to reserve bits for
future address field extension.
Figure 3
also shows the formats of the COLC, COLM, and COLX packets on the COL pins.
Table 6
describes the fields which comprise these packets.
Table 5
Field Description for ROWA Packet and ROWR Packet
Field
Description
DR4T, DR4F
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes
highest device address bit.
DR3 … DR0
BR4 … BR0
Device address for ROWA or ROWR packet.
Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the
RDRAM.
AV
Selects between ROWA packet (AV = 1) and ROWR packet (AV = 0).
R8 … R0
Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM.
ROP10 … ROP0 Opcode field for ROWR packet. Specifies precharge, refresh, and power
management functions.
相關PDF資料
PDF描述
HYB25R128160C 128-MBit Direct RDRAM(128 M位直接RDRAM)
HYB 25M144180C 144-MBit Direct RDRAM(144 M位直接RDRAM)
HYB25R144180C 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
HYB3116160BST-70 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3118160BST-70 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
相關代理商/技術參數(shù)
參數(shù)描述
HYB3116160BSJ 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BSJ-50 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BSJ-60 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BSJ-70 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BST-50 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*