- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄370785 > HYB25M128160C (SIEMENS AG) 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁(yè)數(shù)： | 17/93頁(yè) |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)
Data Book
17
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
ROW-to-ROW Packet Interaction
Figure 6
ROW-to-ROW Packet Interaction-Timing
Figure 6
shows two packets on the ROW pins separated by an interval
t
RRDELAY
which depends
upon the packet contents. No other ROW packets are sent to banks {Ba, Ba+1, Ba-1} between
packet “a” and packet “b” unless noted otherwise.
Table 11
summarizes the
t
RRDELAY
values for all
possible cases.
Cases RR1 through RR4 show two successive ACT commands. In case RR1, there is no restriction
since the ACT commands are to different devices. In case RR2, the
t
RR
restriction applies to the
same device with non-adjacent banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba
needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1 is inserted,
t
RRDELAY
is
t
RC
(
t
RAS
to the PRER
command, and
t
RP
to the next ACT).
Cases RR5 through RR8 show an ACT command followed by a PRER command. In cases RR5 and
RR6, there are no restrictions since the commands are to different devices or to non-adjacent banks
of the same device. In cases RR7 and RR8, the
t
RAS
restriction means the activated bank must wait
before it can be precharged.
Cases RR9 through RR12 show a PRER command followed by an ACT command. In cases RR9
and RR10, there are essentially no restrictions since the commands are to different devices or to
non-adjacent banks of the same device. RR10a and RR10b depend upon whether a bracketed
bank (Ba ± 1) is precharged or activated. In cases RR11 and RR12, the same and adjacent banks
must all wait
t
RP
for the sense amp and bank to precharge before being activated.
Transaction b: ROPb
Transaction a: ROPa
DQB8...0
DQA8...0
b0 = {Db, Bb, Rb}
a0 = {Da, Ba, Ra}
SPT04210
COL4...COL0
ROW2...
ROW0
CTM/CFM
ROPa a0
T0
T1
T3
T2
T4
T17
T11
ROPb b0
T8
RRDELAY
t
T5
T6
T7
T9 T10
T14
T12 T13
T15 T16
T18 T19
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。