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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 45/93頁 |
| 文件大小： | 919K |
| 代理商： | HYB25M128160C |
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Data Book
45
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
4.4. Set Current Control Interval
– This step determines the values of the
t
CCTRL,MAX
RDRAM
timing parameter that are present in the system. The ConfigRMC bus is written with a value
that will be compatible with all RDRAM devices that are present.
4.5. Set Slew Rate Control Interval
– This step determines the values of the
t
TEMP,MAX
RDRAM
timing parameter that are present in the system. The ConfigRMC bus is written with a value
that will be compatible with all RDRAM devices that are present.
4.6. Set Bank/Row/Col Address Bits
– This step determines the number of RDRAM bank,
row, and column address bits that are present in the system. It also determines the RDRAM
core types (independent, doubled, or split) that are present. The ConfigRMC bus is written
with a value that will be compatible with all RDRAM devices that are present.
5. RDRAM Current Control
– This step causes the INIT block to generate a sequence of pulses
which performs RDRAM maintenance operations.
6. RDRAM Core, Read Domain Initialization
– This stage completes the RDRAM initialization
6.1. RDRAM Core Initialization
– A sequence of 192 memory refresh transactions is
performed in order to place the cores of all RDRAMs into the proper operating state.
6.2. RDRAM Read Domain Initialization
- A memory write and memory read transaction is
performed to each RDRAM to determine which read domain each RDRAM occupies. The
programmed delay of each RDRAM is then adjusted so the total RDRAM read delay
(propagation delay plus programmed delay) is constant. The TPARM and TCDLY1
registers of each RDRAM are rewritten with the appropriate read delay values. The
ConfigRMC bus is also rewritten with an updated value.
7. Other RDRAM Register Fields
– This stage rewrites the INIT register with the final values of the
LSR, NSR, and PSR fields.
In essence, the controller must read all the read-only configuration registers of all RDRAMs (or it
must read the SPD device present on each RIMM), it must process this information, and then it must
write all the read-write registers to place the RDRAMs into the proper operating mode.
Initialization Note [1]:
During the initialization process, it is necessary for the controller to perform 128 current control
operations (3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset
or after powerdown (PDN) exit.
Initialization Note [2]:
There are two classes of 64/72Mbit RDRAM. They are distinguished by the “S28IECO” bit in the
SPD. The behavior of the RDRAM at initialization is slightly different for the two types:
S28IECO = 0: Upon powerup the device enters ATTN state. The serial operations SETR, CLRR,
and SETF are performed without requiring a SDEVID match of the SBC bit
(broadcast) to be set.
S28IECO = 1: Upon powerup the device enters PDN state. The serial operations SETR, CLRR,
and SETF require a SDEVID match.
See the document detailing the reference initialization procedure for more information on how to
handle this in a system.
Initialization Note [3]:
After the step of equalizing the total read delay of each RDRAM has been completed (i.e. after the
TCDLY0 and TCDLY1 fields have been written for the final time), a single final memory read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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