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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 21/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
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Data Book
21
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
In cases CC6 through CC10, COPb is a WR command and COPc is a RD command. The
t
CCDELAY
value needed between these two packets depends upon the command and address in the packet
with COPa. In particular, in case CC6 when there is WR-WR-RD command sequence directed to
the same device, a gap will be needed between the packets with COPb and COPc. The gap will
need a COLC packet with a NOCOP command directed to any device in order to force an automatic
retire to take place.
Figure 18
(right) provides a more detailed explanation of this case.
In case CC10, there is a RD-WR-RD sequence directed to the same device. If a prior write to the
same device is unretired when COPa is issued, then a gap will be needed between the packets with
COPb and COPc as in case CC6. The gap will need a COLC packet with a NOCOP command
directed to any device in order to force an automatic retire to take place.
Cases CC7, CC8, and CC9 have no restriction (
t
CCDELAY
is
t
CC
).
For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of
the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also
cause a precharge operation PREC to take place. This precharge may be converted to an
equivalent PRER command on the ROW pins using the rules summarized in
Figure 14
.
Table 13
COL-to-COL Packet Interaction - Rules
Case #
COPa
Da
Ba
Ca1
COPb
Db
Bb
Cb1 COPc
Dc
Bc
Cc1
t
CCDELAY
x…x
t
CC
x…x
t
CC
Example
CC1
xxxx
xxxxx
x…x x…x NOCOP
Db
Bb
Cb1
xxxx
xxxxx
x…x
–
CC2
xxxx
xxxxx
x…x x…x RD,WR
Db
Bb
Cb1
NOCOP
xxxxx
x…x
–
CC3
xxxx
xxxxx
x…x x…x RD
Db
Bb
Cb1
WR
xxxxx
x…x
x…x
t
CC
+
t
CAC
-
t
CWD
x…x
t
CC
x…x
t
CC
x…x
t
RTR
x…x
t
CC
x…x
t
CC
x…x
t
CC
Figure 4
CC4
xxxx
xxxxx
x…x x…x RD
Db
Bb
Cb1
RD
xxxxx
x…x
Figure 15
CC5
xxxx
xxxxx
x…x x…x WR
Db
Bb
Cb1
WR
xxxxx
x…x
Figure 16
CC6
WR
== Db
x
x…x WR
Db
Bb
Cb1
RD
== Db
x…x
Figure 18
CC7
WR
== Db
x
x…x WR
Db
Bb
Cb1
RD
/= Db
x…x
–
CC8
WR
/= Db
x
x…x WR
Db
Bb
Cb1
RD
== Db
x…x
–
CC9
NOCOP
== Db
x
x…x WR
Db
Bb
Cb1
RD
== Db
x…x
–
CC10
RD
== Db
x
x…x WR
Db
Bb
Cb1
RD
== Db
x…x
x…x
t
CC
–
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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