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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 26/93頁 |
| 文件大小： | 919K |
| 代理商： | HYB25M128160C |
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Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
26
2.00
Figure 12
Row Packet Examples
Row and Column Cycle Description
Activate:
A row cycle begins with the activate (ACT) operation. The activation process is
destructive; the act of sensing the value of a bit in a bank’s storage cell transfers the bit to the sense
amp, but leaves the original bit in the storage cell with an incorrect value.
Restore:
Because the activation process is destructive, a hidden operation called restore is
automatically performed. The restore operation rewrites the bits in the sense amp back into the
storage cells of the activated row of the bank.
Read/Write:
While the restore operation takes place, the sense amp may be read (RD) and written
(WR) using column operations. If new data is written into the sense amp, it is automatically
forwarded to the storage cells of the bank so the data in the activated row and the data in the sense
amp remain identical.
Precharge:
When both the restore operation and the column operations are completed, the sense
amp and bank are precharged (PRE). This leaves them in the proper state to begin another activate
operation.
Intervals:
The activate operation requires the interval
t
RCD,MIN
to complete. The hidden restore
operation requires the interval
t
RAS,MIN
–
t
RCD,MIN
to complete. Column read and write operations are
also performed during the
t
RAS,MIN
–
t
RCD,MIN
interval (if more than about four column operations are
COL4...COL0
DQB8...0
DQA8...0
SPA04216
T24
Same Device
Same Device
Different Device
Same Device
Same Device
Different Device
PRER b0
ROW2...
ROW0
CTM/CFM
PRER a0
PACKET
t
T2
T0
T1
T3
T4
T14
PRER a0
T7
T5
T6
T8
T11
T13
T12
t
PRER c0
PP
T19
T15 T16
T18
T17
T20 T21
T23
T22
c0 = {Da, Ba+1, Rc}
b0 = {Db, Bb, Rb}
c0 = {Da, Bc, Rc}
c0 = {Da, Ba, Rc}
c0 = {Da, Bc, Rc}
b0 = {Db, Bb, Rb}
a0 = {Da, Ba, Ra}
Any Bank
Non-adjacent Bank
T34
ACT b0
PRER a0
PACKET
t
T29
T27 T28
T30 T31 T32 T33
PRER a0
PACKET
t
T39
T36
T35
RR10
T41
T40
T42 T43
Non-adjacent Bank
Adjacent Bank
Any Bank
Same Bank
RR13
RR14
RR15
RR16
RR9
ACT c0
T46
T45
T44
T47
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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