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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 24/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
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Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
24
2.00
ROW-to-ROW Examples
Figure 10
shows examples of some of the ROW-to-ROW packet spacings from
Table 11
. A
complete sequence of activate and precharge commands is directed to a bank. The RR8 and RR12
rules apply to this sequence. In addition to satisfying the
t
RAS
and
t
RP
timing parameters, the
separation between ACT commands to the same bank must also satisfy the
t
RC
timing parameter
(RR4).
When a bank is activated, it is necessary for adjacent banks to remain precharged. As a result, the
adjacent banks will also satisfy parallel timing constraints; in the example, the RR11 and RR3 rules
are analogous to the RR12 and RR4 rules.
Figure 10
Row Packet Example
Figure 11
shows examples of the ACT-to-ACT (RR1, RR2) and ACT-to-PRER (RR5, RR6)
command spacings from
Table 11
. In general, the commands in ROW packets may be spaced an
interval
t
PACKET
apart unless they are directed to the same or adjacent banks or unless they are a
similar command type (both PRER or both ACT) directed to the same device.
DQA8...0
DQB8...0
COL4...COL0
t
RC
SPA04214
T24
Same Device
Same Device
Same Device
Same Device
Same Device
ROW0
CTM/CFM
ROW2...
ACT a0
T2
T0
T1
T3
T4
T14
T7
T5
T6
T8
T9
T10 T11
T13
T12
RAS
t
T19
T15 T16
T18
T17
T20 T21
T23
T22
a0 = {Da, Ba, Ra}
a1 = {Da, Ba+1}
b0 = {Da, Ba+1, Rb}
b0 = {Da, Ba, Rb}
b0 = {Da, Ba, Rb}
b0 = {Da, Ba+1, Rb}
RR11
RR12
Adjacent Bank
Same Bank
T34
ACT b0
PRER a1
RP
t
T29
T25 T26 T27 T28
T30 T31 T32 T33
T39
T36
T35
T37 T38
T41
T40
T42 T43
RR7
RR3
RR4
Adjacent Bank
Adjacent Bank
Same Bank
T46
T45
T44
T47
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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