參數(shù)資料
型號: HYB25M128160C
廠商: SIEMENS AG
英文描述: 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM)
中文描述: 128 - Mbit的直接的RDRAM(128兆直接的RDRAM)
文件頁數(shù): 72/93頁
文件大?。?/td> 919K
代理商: HYB25M128160C
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
72
2.00
RSL - Clocking
Figure 53
is a timing diagram which shows the detailed requirements for the RSL clock signals on
the Channel.
The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and
DQB, outputs. Most timing is measured relative to the points where they cross. The
t
CYCLE
parameter is measured from the falling CTM edge to the falling CTM edge. The
t
CL
and
t
CH
parameters are measured from falling to rising and rising to falling edges of CTM. The
t
CR
and
t
CF
rise- and fall-time parameters are measured at the 20% and 80% points.
t
AS
t
SA
t
ASN
t
ASP
ATTN-to-STBY power state delay
1
t
CYCLE
t
CYCLE
t
CYCLE
t
CYCLE
Figure 46
STBY-to-ATTN power state delay
0
Figure 46
ATTN/STBY-to-NAP power state delay
8
Figure 47
ATTN/STBY-to-PDN power state delay
8
Figure 47
1)
This parameter also applies to a -800 or -711 part when operated with
t
CYCLE
= 3.33 ns.
This parameter also applies to a -800 part when operated with
t
CYCLE
= 2.81 ns.
3)
t
and
t
Q,MAX
for other
t
CYCLE
values can be interpolated between or extrapolated from the timings at the
3 specified t
CYCLE
values.
2)
Table 22
Timing Characteristics
(cont’d)
Parameter Symbol
Limit Values
Unit
Figure
min.
max.
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