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參數(shù)資料
| 型號： | HYB25M128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128兆直接的RDRAM） |
| 文件頁數(shù)： | 30/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25M128160C |
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Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
30
2.00
Read Transaction - Example
Figure 15
shows an example of a read transaction. It begins by activating a bank with an ACT a0
command in an ROWA packet. A time
t
RCD
later a RD a1 command is issued in a COLC packet.
Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while
the RD command includes device, bank, and column address (abbreviated as a1). A time
t
CAC
after
the RD command the read data dualoct Q(a1) is returned by the device. Note that the packets on
the ROW and COL pins use the end of the packet as a timing reference point, while the packets on
the DQA/DQB pins use the beginning of the packet as a timing reference point.
A time
t
CC
after the first COLC packet on the COL pins a second is issued. It contains a RD a2
command. The a2 address has the same device and bank address as the a1 address (and a0
address), but a different column address. A time
t
CAC
after the second RD command a second read
data dualoct Q(a2) is returned by the device.
Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank
to precharge so that a different row may be activated in a subsequent transaction or so that an
adjacent bank may be activated. The a3 address includes the same device and bank address as the
a0, a1, and a2 addresses. The PRER command must occur a time
t
RAS
or more after the original
ACT command (the activation operation in any DRAM is destructive, and the contents of the
selected row must be restored from the two associated sense amps of the bank during the
t
RAS
interval). The PRER command must also occur a time
t
RDP
or more after the last RD command. Note
that the
t
RDP
value shown is greater than the
t
RDP,MIN
specification in
Table 23
. This transaction
example reads two dualocts, but there is actually enough time to read three dualocts before
t
RDP
becomes the limiting parameter rather than
t
RAS
. If four dualocts were read, the packet with PRER
would need to shift right (be delayed) by one
t
CYCLE
(note - this case is not shown).
Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT
command must occur a time
t
RC
or more after the first ACT command and a time
t
RP
or more after
the PRER command. This ensures that the bank and its associated sense amps are precharged.
This example assumes that the second transaction has the same device and bank address as the
first transaction, but a different row address. Transaction b may not be started until transaction a has
finished. However, transactions to other banks or other devices may be issued during transaction a
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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