參數(shù)資料
型號： HYB25M128160C
廠商： SIEMENS AG
英文描述： 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM)
中文描述： 128 - Mbit的直接的RDRAM（128兆直接的RDRAM）
文件頁數(shù)： 42/93頁
文件大小： 919K
代理商： HYB25M128160C
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
42
2.00
Table 16
Field Description for Control Register Packets
Field
Description
rsrv
Reserved. Should be driven as “0” by controller.
SOP3 … SOP0
0000 - SRD. Serial read of control register {SA11 … SA0} of RDRAM
{SDEV5 … SDEV0}.
0001 - SWR. Serial write of control register {SA11 … SA0} of RDRAM
{SDEV5 … SDEV0}.
0010 - SETR. Set Reset bit, all control registers assume their reset values.
1)
16
t
SCYCLE
delay until CLRR command.
0100 - SETF. Set fast (normal) clock mode. 4
t
SCYCLE
delay until next
command.
1011 - CLRR. Clear Reset bit, all control registers retain their reset values.
1)
4
t
SCYCLE
delay until next command.
1111 - NOP. No serial operation.
0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings.
SDEV5 …
SDEV0
SBC
Serial device. Compared to SDEVID5…SDEVID0 field of INIT control register
field to select the RDRAM to which the transaction is directed.
Serial broadcast. When set, RDRAMs ignore {SDEV5 … SDEV0} for
RDRAM selection.
SA11…SA0
Serial address. Selects which control register of the selected RDRAM is read
or written.
SD15…SD0
Serial data. The 16 bits of data written to or read from the selected control
register of the selected RDRAM.
1)
The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they
may not be used in isolation. This is called “SETR/CLRR Reset”.
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