參數(shù)資料
型號(hào)： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 86/92頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計(jì)資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
Data Sheet
ADuC7039
Rev. D | Page 87 of 92
Table 62. LINSTA MMR Bit Designations
Bits
Description
15 to 11
Reserved.
10
LIN wake-up interrupt.
This bit is set if LIN woke up the ADuC7039. The wake-up functionality (LINWU MMR) is only used when POWCON[3] = 0.
This bit is cleared automatically by a read of the LINSTA MMR.
9
Break time maximum.
This bit is 0 if the first break symbol after enabling the LIN interface has ended before maximum count reached.
This bit is 1 if the first break symbol after enabling the LIN interface has ended after maximum count reached.
This bit is cleared automatically by hardware when reading LINSTA MMR.
This bit is only valid on the first break symbol after enabling the LIN peripheral via LINCON[11].
8
PID parity error.
This bit is set automatically by hardware if the current byte in the LINDAT register does not correctly match the parity scheme for
a PID as described in the LIN 2.1 specifications.
This bit is cleared by hardware if the current byte in the LINDAT register correctly matches the parity scheme for a PID.
It is left to the user to determine when a PID is actually in the data register. The parity check is done whether a PID or data byte is
in the LINDAT MMR.
7
Checksum match.
This bit is only valid when LINSTA[0] = 1.
This bit is set automatically if the value in LINCS does not match the received data in LINDAT.
This bit is cleared on a read of the LINSTA MMR or when LINDAT and LINCS match while LINSTA[0] = 1.
6
Frame error.
This bit is 0 if there is no frame error. It is cleared automatically by a read of LINSTA.
This bit is 1 if a frame error has occurred during reception of a data byte, that is, a valid stop was not detected.
5
Negative edge maximum error interrupt (maskable).
This bit is 0 if the number of negative edges allowed in a frame is not surpassed.
This bit is 1 if the number of negative edges is 57 or more.
This bit is cleared automatically by hardware when reading LINSTA MMR.
4
LIN collision detect interrupt (maskable).
This bit is set automatically by hardware if the device has stopped transmission due to a collision on the bus. This bit is not set
if the collision detect and transmit complete interrupt is enabled (LINCON[6] = 0) and the transmit complete interrupt bit is set
(LINSTA[2] = 1).
This bit is cleared automatically by hardware when reading LINSTA MMR.
3
Break receive interrupt (maskable).
This bit is 0 if no valid break symbol has been received.
This bit is 1 if a low time of 11 nominal bits is detected on the LIN bus. This bit is cleared automatically on reading the LINSTA MMR.
2
Transmit complete interrupt (maskable).
This bit is 0 if data is still in the LINDAT register.
This bit is 1 when all data is transmitted. It remains set to 1 until the LIN receives a break symbol. It is cleared automatically in
receive mode.
1
Transmit ready interrupt (maskable).
This bit is 0 if the previous data written in the LINDAT MMR is still in the LINDAT and has not being shifted to the transmit
register. Writing data to the LINDAT MMR while the transmit ready bit is 0 overwrites the previous byte to be transmitted.
This bit is 1 if the previous data written in the LINDAT MMR is now in the transmit register.
0
Receive ready interrupt.
This bit is 0 if there is no new data to read in the LINDAT MMR.
This bit is 1 if there is new data to read in the LINDAT MMR. Reading the LINDAT MMR clears this bit.
相關(guān)PDF資料
PDF描述
EYM15DRSH CONN EDGECARD 30POS DIP .156 SLD
AIUR-06-102K INDUCTOR POWER 1000UH 10% T/H
V300C3V3C50B2 CONVERTER MOD DC/DC 3.3V 50W
EGM15DRSH CONN EDGECARD 30POS DIP .156 SLD
EVAL-ADUC7023QSPZ1 BOARD EVAL FOR ADUC7023
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADUC7060QSPZ 功能描述:KIT DEV QUICK START ADUC7060 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
EVAL-ADUC7060QSPZU1 制造商:Analog Devices 功能描述:
EVALADUC7060QSPZU2 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits)
EVAL-ADUC7061MKZ 功能描述:開發(fā)板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評(píng)估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V
EVAL-ADUC7061MKZ 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*